233 lines
6.0 KiB
C
233 lines
6.0 KiB
C
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/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Kevin Tian <kevin.tian@intel.com>
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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* Contributors:
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* Min he <min.he@intel.com>
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*
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*/
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#ifndef _GVT_INTERRUPT_H_
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#define _GVT_INTERRUPT_H_
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#include <linux/hrtimer.h>
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#include <linux/kernel.h>
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#include "i915_reg_defs.h"
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enum intel_gvt_event_type {
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RCS_MI_USER_INTERRUPT = 0,
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RCS_DEBUG,
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RCS_MMIO_SYNC_FLUSH,
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RCS_CMD_STREAMER_ERR,
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RCS_PIPE_CONTROL,
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RCS_L3_PARITY_ERR,
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RCS_WATCHDOG_EXCEEDED,
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RCS_PAGE_DIRECTORY_FAULT,
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RCS_AS_CONTEXT_SWITCH,
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RCS_MONITOR_BUFF_HALF_FULL,
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VCS_MI_USER_INTERRUPT,
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VCS_MMIO_SYNC_FLUSH,
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VCS_CMD_STREAMER_ERR,
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VCS_MI_FLUSH_DW,
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VCS_WATCHDOG_EXCEEDED,
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VCS_PAGE_DIRECTORY_FAULT,
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VCS_AS_CONTEXT_SWITCH,
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VCS2_MI_USER_INTERRUPT,
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VCS2_MI_FLUSH_DW,
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VCS2_AS_CONTEXT_SWITCH,
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BCS_MI_USER_INTERRUPT,
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BCS_MMIO_SYNC_FLUSH,
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BCS_CMD_STREAMER_ERR,
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BCS_MI_FLUSH_DW,
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BCS_PAGE_DIRECTORY_FAULT,
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BCS_AS_CONTEXT_SWITCH,
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VECS_MI_USER_INTERRUPT,
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VECS_MI_FLUSH_DW,
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VECS_AS_CONTEXT_SWITCH,
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PIPE_A_FIFO_UNDERRUN,
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PIPE_B_FIFO_UNDERRUN,
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PIPE_A_CRC_ERR,
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PIPE_B_CRC_ERR,
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PIPE_A_CRC_DONE,
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PIPE_B_CRC_DONE,
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PIPE_A_ODD_FIELD,
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PIPE_B_ODD_FIELD,
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PIPE_A_EVEN_FIELD,
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PIPE_B_EVEN_FIELD,
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PIPE_A_LINE_COMPARE,
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PIPE_B_LINE_COMPARE,
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PIPE_C_LINE_COMPARE,
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PIPE_A_VBLANK,
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PIPE_B_VBLANK,
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PIPE_C_VBLANK,
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PIPE_A_VSYNC,
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PIPE_B_VSYNC,
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PIPE_C_VSYNC,
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PRIMARY_A_FLIP_DONE,
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PRIMARY_B_FLIP_DONE,
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PRIMARY_C_FLIP_DONE,
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SPRITE_A_FLIP_DONE,
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SPRITE_B_FLIP_DONE,
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SPRITE_C_FLIP_DONE,
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PCU_THERMAL,
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PCU_PCODE2DRIVER_MAILBOX,
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DPST_PHASE_IN,
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DPST_HISTOGRAM,
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GSE,
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DP_A_HOTPLUG,
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AUX_CHANNEL_A,
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PERF_COUNTER,
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POISON,
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GTT_FAULT,
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ERROR_INTERRUPT_COMBINED,
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FDI_RX_INTERRUPTS_TRANSCODER_A,
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AUDIO_CP_CHANGE_TRANSCODER_A,
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AUDIO_CP_REQUEST_TRANSCODER_A,
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FDI_RX_INTERRUPTS_TRANSCODER_B,
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AUDIO_CP_CHANGE_TRANSCODER_B,
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AUDIO_CP_REQUEST_TRANSCODER_B,
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FDI_RX_INTERRUPTS_TRANSCODER_C,
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AUDIO_CP_CHANGE_TRANSCODER_C,
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AUDIO_CP_REQUEST_TRANSCODER_C,
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ERR_AND_DBG,
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GMBUS,
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SDVO_B_HOTPLUG,
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CRT_HOTPLUG,
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DP_B_HOTPLUG,
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DP_C_HOTPLUG,
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DP_D_HOTPLUG,
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AUX_CHANNEL_B,
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AUX_CHANNEL_C,
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AUX_CHANNEL_D,
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AUDIO_POWER_STATE_CHANGE_B,
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AUDIO_POWER_STATE_CHANGE_C,
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AUDIO_POWER_STATE_CHANGE_D,
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INTEL_GVT_EVENT_RESERVED,
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INTEL_GVT_EVENT_MAX,
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};
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struct intel_gvt_irq;
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struct intel_gvt;
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struct intel_vgpu;
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typedef void (*gvt_event_virt_handler_t)(struct intel_gvt_irq *irq,
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enum intel_gvt_event_type event, struct intel_vgpu *vgpu);
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struct intel_gvt_irq_ops {
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void (*init_irq)(struct intel_gvt_irq *irq);
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void (*check_pending_irq)(struct intel_vgpu *vgpu);
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};
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/* the list of physical interrupt control register groups */
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enum intel_gvt_irq_type {
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INTEL_GVT_IRQ_INFO_GT,
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INTEL_GVT_IRQ_INFO_DPY,
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INTEL_GVT_IRQ_INFO_PCH,
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INTEL_GVT_IRQ_INFO_PM,
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INTEL_GVT_IRQ_INFO_MASTER,
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INTEL_GVT_IRQ_INFO_GT0,
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INTEL_GVT_IRQ_INFO_GT1,
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INTEL_GVT_IRQ_INFO_GT2,
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INTEL_GVT_IRQ_INFO_GT3,
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INTEL_GVT_IRQ_INFO_DE_PIPE_A,
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INTEL_GVT_IRQ_INFO_DE_PIPE_B,
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INTEL_GVT_IRQ_INFO_DE_PIPE_C,
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INTEL_GVT_IRQ_INFO_DE_PORT,
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INTEL_GVT_IRQ_INFO_DE_MISC,
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INTEL_GVT_IRQ_INFO_AUD,
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INTEL_GVT_IRQ_INFO_PCU,
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INTEL_GVT_IRQ_INFO_MAX,
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};
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#define INTEL_GVT_IRQ_BITWIDTH 32
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/* device specific interrupt bit definitions */
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struct intel_gvt_irq_info {
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char *name;
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i915_reg_t reg_base;
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enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH];
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unsigned long warned;
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int group;
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DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH);
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bool has_upstream_irq;
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};
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/* per-event information */
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struct intel_gvt_event_info {
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int bit; /* map to register bit */
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int policy; /* forwarding policy */
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struct intel_gvt_irq_info *info; /* register info */
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gvt_event_virt_handler_t v_handler; /* for v_event */
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};
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struct intel_gvt_irq_map {
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int up_irq_group;
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int up_irq_bit;
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int down_irq_group;
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u32 down_irq_bitmask;
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};
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/* structure containing device specific IRQ state */
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struct intel_gvt_irq {
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const struct intel_gvt_irq_ops *ops;
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struct intel_gvt_irq_info *info[INTEL_GVT_IRQ_INFO_MAX];
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DECLARE_BITMAP(irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX);
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struct intel_gvt_event_info events[INTEL_GVT_EVENT_MAX];
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DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX);
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struct intel_gvt_irq_map *irq_map;
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};
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int intel_gvt_init_irq(struct intel_gvt *gvt);
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void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
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enum intel_gvt_event_type event);
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int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
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void *p_data, unsigned int bytes);
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int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
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unsigned int reg, void *p_data, unsigned int bytes);
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int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
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unsigned int reg, void *p_data, unsigned int bytes);
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int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
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unsigned int reg, void *p_data, unsigned int bytes);
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int gvt_ring_id_to_pipe_control_notify_event(int ring_id);
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int gvt_ring_id_to_mi_flush_dw_event(int ring_id);
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int gvt_ring_id_to_mi_user_interrupt_event(int ring_id);
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#endif /* _GVT_INTERRUPT_H_ */
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