573 lines
13 KiB
C
573 lines
13 KiB
C
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#include <linux/string_helpers.h>
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_dram.h"
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#include "intel_mchbar_regs.h"
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#include "intel_pcode.h"
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struct dram_dimm_info {
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u16 size;
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u8 width, ranks;
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};
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struct dram_channel_info {
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struct dram_dimm_info dimm_l, dimm_s;
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u8 ranks;
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bool is_16gb_dimm;
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};
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#define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
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static const char *intel_dram_type_str(enum intel_dram_type type)
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{
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static const char * const str[] = {
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DRAM_TYPE_STR(UNKNOWN),
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DRAM_TYPE_STR(DDR3),
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DRAM_TYPE_STR(DDR4),
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DRAM_TYPE_STR(LPDDR3),
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DRAM_TYPE_STR(LPDDR4),
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};
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if (type >= ARRAY_SIZE(str))
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type = INTEL_DRAM_UNKNOWN;
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return str[type];
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}
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#undef DRAM_TYPE_STR
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static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
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{
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return dimm->ranks * 64 / (dimm->width ?: 1);
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}
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/* Returns total Gb for the whole DIMM */
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static int skl_get_dimm_size(u16 val)
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{
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return (val & SKL_DRAM_SIZE_MASK) * 8;
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}
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static int skl_get_dimm_width(u16 val)
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{
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if (skl_get_dimm_size(val) == 0)
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return 0;
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switch (val & SKL_DRAM_WIDTH_MASK) {
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case SKL_DRAM_WIDTH_X8:
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case SKL_DRAM_WIDTH_X16:
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case SKL_DRAM_WIDTH_X32:
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val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
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return 8 << val;
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default:
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MISSING_CASE(val);
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return 0;
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}
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}
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static int skl_get_dimm_ranks(u16 val)
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{
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if (skl_get_dimm_size(val) == 0)
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return 0;
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val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
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return val + 1;
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}
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/* Returns total Gb for the whole DIMM */
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static int icl_get_dimm_size(u16 val)
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{
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return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
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}
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static int icl_get_dimm_width(u16 val)
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{
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if (icl_get_dimm_size(val) == 0)
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return 0;
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switch (val & ICL_DRAM_WIDTH_MASK) {
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case ICL_DRAM_WIDTH_X8:
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case ICL_DRAM_WIDTH_X16:
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case ICL_DRAM_WIDTH_X32:
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val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
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return 8 << val;
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default:
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MISSING_CASE(val);
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return 0;
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}
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}
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static int icl_get_dimm_ranks(u16 val)
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{
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if (icl_get_dimm_size(val) == 0)
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return 0;
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val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
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return val + 1;
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}
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static bool
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skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
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{
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/* Convert total Gb to Gb per DRAM device */
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return dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
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}
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static void
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skl_dram_get_dimm_info(struct drm_i915_private *i915,
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struct dram_dimm_info *dimm,
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int channel, char dimm_name, u16 val)
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{
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if (GRAPHICS_VER(i915) >= 11) {
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dimm->size = icl_get_dimm_size(val);
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dimm->width = icl_get_dimm_width(val);
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dimm->ranks = icl_get_dimm_ranks(val);
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} else {
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dimm->size = skl_get_dimm_size(val);
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dimm->width = skl_get_dimm_width(val);
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dimm->ranks = skl_get_dimm_ranks(val);
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}
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drm_dbg_kms(&i915->drm,
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"CH%u DIMM %c size: %u Gb, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
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channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
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str_yes_no(skl_is_16gb_dimm(dimm)));
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}
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static int
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skl_dram_get_channel_info(struct drm_i915_private *i915,
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struct dram_channel_info *ch,
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int channel, u32 val)
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{
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skl_dram_get_dimm_info(i915, &ch->dimm_l,
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channel, 'L', val & 0xffff);
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skl_dram_get_dimm_info(i915, &ch->dimm_s,
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channel, 'S', val >> 16);
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if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
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drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel);
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return -EINVAL;
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}
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if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
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ch->ranks = 2;
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else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
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ch->ranks = 2;
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else
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ch->ranks = 1;
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ch->is_16gb_dimm = skl_is_16gb_dimm(&ch->dimm_l) ||
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skl_is_16gb_dimm(&ch->dimm_s);
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drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n",
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channel, ch->ranks, str_yes_no(ch->is_16gb_dimm));
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return 0;
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}
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static bool
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intel_is_dram_symmetric(const struct dram_channel_info *ch0,
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const struct dram_channel_info *ch1)
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{
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return !memcmp(ch0, ch1, sizeof(*ch0)) &&
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(ch0->dimm_s.size == 0 ||
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!memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
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}
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static int
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skl_dram_get_channels_info(struct drm_i915_private *i915)
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{
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struct dram_info *dram_info = &i915->dram_info;
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struct dram_channel_info ch0 = {}, ch1 = {};
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u32 val;
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int ret;
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val = intel_uncore_read(&i915->uncore,
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SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
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ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
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if (ret == 0)
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dram_info->num_channels++;
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val = intel_uncore_read(&i915->uncore,
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SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
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ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
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if (ret == 0)
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dram_info->num_channels++;
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if (dram_info->num_channels == 0) {
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drm_info(&i915->drm, "Number of memory channels is zero\n");
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return -EINVAL;
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}
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if (ch0.ranks == 0 && ch1.ranks == 0) {
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drm_info(&i915->drm, "couldn't get memory rank information\n");
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return -EINVAL;
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}
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dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
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dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
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drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n",
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str_yes_no(dram_info->symmetric_memory));
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return 0;
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}
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static enum intel_dram_type
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skl_get_dram_type(struct drm_i915_private *i915)
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{
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u32 val;
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val = intel_uncore_read(&i915->uncore,
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SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
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switch (val & SKL_DRAM_DDR_TYPE_MASK) {
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case SKL_DRAM_DDR_TYPE_DDR3:
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return INTEL_DRAM_DDR3;
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case SKL_DRAM_DDR_TYPE_DDR4:
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return INTEL_DRAM_DDR4;
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case SKL_DRAM_DDR_TYPE_LPDDR3:
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return INTEL_DRAM_LPDDR3;
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case SKL_DRAM_DDR_TYPE_LPDDR4:
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return INTEL_DRAM_LPDDR4;
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default:
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MISSING_CASE(val);
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return INTEL_DRAM_UNKNOWN;
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}
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}
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static int
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skl_get_dram_info(struct drm_i915_private *i915)
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{
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struct dram_info *dram_info = &i915->dram_info;
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int ret;
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dram_info->type = skl_get_dram_type(i915);
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drm_dbg_kms(&i915->drm, "DRAM type: %s\n",
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intel_dram_type_str(dram_info->type));
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ret = skl_dram_get_channels_info(i915);
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if (ret)
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return ret;
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return 0;
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}
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/* Returns Gb per DRAM device */
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static int bxt_get_dimm_size(u32 val)
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{
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switch (val & BXT_DRAM_SIZE_MASK) {
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case BXT_DRAM_SIZE_4GBIT:
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return 4;
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case BXT_DRAM_SIZE_6GBIT:
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return 6;
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case BXT_DRAM_SIZE_8GBIT:
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return 8;
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case BXT_DRAM_SIZE_12GBIT:
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return 12;
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case BXT_DRAM_SIZE_16GBIT:
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return 16;
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default:
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MISSING_CASE(val);
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return 0;
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}
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}
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static int bxt_get_dimm_width(u32 val)
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{
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if (!bxt_get_dimm_size(val))
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return 0;
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val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
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return 8 << val;
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}
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static int bxt_get_dimm_ranks(u32 val)
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{
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if (!bxt_get_dimm_size(val))
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return 0;
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switch (val & BXT_DRAM_RANK_MASK) {
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case BXT_DRAM_RANK_SINGLE:
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return 1;
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case BXT_DRAM_RANK_DUAL:
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return 2;
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default:
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MISSING_CASE(val);
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return 0;
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}
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}
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static enum intel_dram_type bxt_get_dimm_type(u32 val)
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{
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if (!bxt_get_dimm_size(val))
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return INTEL_DRAM_UNKNOWN;
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switch (val & BXT_DRAM_TYPE_MASK) {
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case BXT_DRAM_TYPE_DDR3:
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return INTEL_DRAM_DDR3;
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case BXT_DRAM_TYPE_LPDDR3:
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return INTEL_DRAM_LPDDR3;
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case BXT_DRAM_TYPE_DDR4:
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return INTEL_DRAM_DDR4;
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case BXT_DRAM_TYPE_LPDDR4:
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return INTEL_DRAM_LPDDR4;
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default:
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MISSING_CASE(val);
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return INTEL_DRAM_UNKNOWN;
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}
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}
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static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val)
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{
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dimm->width = bxt_get_dimm_width(val);
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dimm->ranks = bxt_get_dimm_ranks(val);
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/*
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* Size in register is Gb per DRAM device. Convert to total
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* Gb to match the way we report this for non-LP platforms.
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*/
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dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm);
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}
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static int bxt_get_dram_info(struct drm_i915_private *i915)
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{
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struct dram_info *dram_info = &i915->dram_info;
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u32 val;
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u8 valid_ranks = 0;
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int i;
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/*
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* Now read each DUNIT8/9/10/11 to check the rank of each dimms.
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*/
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for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
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struct dram_dimm_info dimm;
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enum intel_dram_type type;
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val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i));
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if (val == 0xFFFFFFFF)
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continue;
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dram_info->num_channels++;
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bxt_get_dimm_info(&dimm, val);
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type = bxt_get_dimm_type(val);
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||
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|
|
||
|
|
drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN &&
|
||
|
|
dram_info->type != INTEL_DRAM_UNKNOWN &&
|
||
|
|
dram_info->type != type);
|
||
|
|
|
||
|
|
drm_dbg_kms(&i915->drm,
|
||
|
|
"CH%u DIMM size: %u Gb, width: X%u, ranks: %u, type: %s\n",
|
||
|
|
i - BXT_D_CR_DRP0_DUNIT_START,
|
||
|
|
dimm.size, dimm.width, dimm.ranks,
|
||
|
|
intel_dram_type_str(type));
|
||
|
|
|
||
|
|
if (valid_ranks == 0)
|
||
|
|
valid_ranks = dimm.ranks;
|
||
|
|
|
||
|
|
if (type != INTEL_DRAM_UNKNOWN)
|
||
|
|
dram_info->type = type;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) {
|
||
|
|
drm_info(&i915->drm, "couldn't get memory information\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
|
||
|
|
{
|
||
|
|
struct dram_info *dram_info = &dev_priv->dram_info;
|
||
|
|
u32 val = 0;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
|
||
|
|
ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
if (GRAPHICS_VER(dev_priv) == 12) {
|
||
|
|
switch (val & 0xf) {
|
||
|
|
case 0:
|
||
|
|
dram_info->type = INTEL_DRAM_DDR4;
|
||
|
|
break;
|
||
|
|
case 1:
|
||
|
|
dram_info->type = INTEL_DRAM_DDR5;
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
dram_info->type = INTEL_DRAM_LPDDR5;
|
||
|
|
break;
|
||
|
|
case 3:
|
||
|
|
dram_info->type = INTEL_DRAM_LPDDR4;
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
dram_info->type = INTEL_DRAM_DDR3;
|
||
|
|
break;
|
||
|
|
case 5:
|
||
|
|
dram_info->type = INTEL_DRAM_LPDDR3;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
MISSING_CASE(val & 0xf);
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
switch (val & 0xf) {
|
||
|
|
case 0:
|
||
|
|
dram_info->type = INTEL_DRAM_DDR4;
|
||
|
|
break;
|
||
|
|
case 1:
|
||
|
|
dram_info->type = INTEL_DRAM_DDR3;
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
dram_info->type = INTEL_DRAM_LPDDR3;
|
||
|
|
break;
|
||
|
|
case 3:
|
||
|
|
dram_info->type = INTEL_DRAM_LPDDR4;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
MISSING_CASE(val & 0xf);
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
dram_info->num_channels = (val & 0xf0) >> 4;
|
||
|
|
dram_info->num_qgv_points = (val & 0xf00) >> 8;
|
||
|
|
dram_info->num_psf_gv_points = (val & 0x3000) >> 12;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int gen11_get_dram_info(struct drm_i915_private *i915)
|
||
|
|
{
|
||
|
|
int ret = skl_get_dram_info(i915);
|
||
|
|
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
return icl_pcode_read_mem_global_info(i915);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int gen12_get_dram_info(struct drm_i915_private *i915)
|
||
|
|
{
|
||
|
|
i915->dram_info.wm_lv_0_adjust_needed = false;
|
||
|
|
|
||
|
|
return icl_pcode_read_mem_global_info(i915);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int xelpdp_get_dram_info(struct drm_i915_private *i915)
|
||
|
|
{
|
||
|
|
u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
|
||
|
|
struct dram_info *dram_info = &i915->dram_info;
|
||
|
|
|
||
|
|
switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
|
||
|
|
case 0:
|
||
|
|
dram_info->type = INTEL_DRAM_DDR4;
|
||
|
|
break;
|
||
|
|
case 1:
|
||
|
|
dram_info->type = INTEL_DRAM_DDR5;
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
dram_info->type = INTEL_DRAM_LPDDR5;
|
||
|
|
break;
|
||
|
|
case 3:
|
||
|
|
dram_info->type = INTEL_DRAM_LPDDR4;
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
dram_info->type = INTEL_DRAM_DDR3;
|
||
|
|
break;
|
||
|
|
case 5:
|
||
|
|
dram_info->type = INTEL_DRAM_LPDDR3;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
MISSING_CASE(val);
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val);
|
||
|
|
dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
|
||
|
|
/* PSF GV points not supported in D14+ */
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void intel_dram_detect(struct drm_i915_private *i915)
|
||
|
|
{
|
||
|
|
struct dram_info *dram_info = &i915->dram_info;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))
|
||
|
|
return;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Assume level 0 watermark latency adjustment is needed until proven
|
||
|
|
* otherwise, this w/a is not needed by bxt/glk.
|
||
|
|
*/
|
||
|
|
dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);
|
||
|
|
|
||
|
|
if (DISPLAY_VER(i915) >= 14)
|
||
|
|
ret = xelpdp_get_dram_info(i915);
|
||
|
|
else if (GRAPHICS_VER(i915) >= 12)
|
||
|
|
ret = gen12_get_dram_info(i915);
|
||
|
|
else if (GRAPHICS_VER(i915) >= 11)
|
||
|
|
ret = gen11_get_dram_info(i915);
|
||
|
|
else if (IS_GEN9_LP(i915))
|
||
|
|
ret = bxt_get_dram_info(i915);
|
||
|
|
else
|
||
|
|
ret = skl_get_dram_info(i915);
|
||
|
|
if (ret)
|
||
|
|
return;
|
||
|
|
|
||
|
|
drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);
|
||
|
|
|
||
|
|
drm_dbg_kms(&i915->drm, "Watermark level 0 adjustment needed: %s\n",
|
||
|
|
str_yes_no(dram_info->wm_lv_0_adjust_needed));
|
||
|
|
}
|
||
|
|
|
||
|
|
static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
|
||
|
|
{
|
||
|
|
static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
|
||
|
|
static const u8 sets[4] = { 1, 1, 2, 2 };
|
||
|
|
|
||
|
|
return EDRAM_NUM_BANKS(cap) *
|
||
|
|
ways[EDRAM_WAYS_IDX(cap)] *
|
||
|
|
sets[EDRAM_SETS_IDX(cap)];
|
||
|
|
}
|
||
|
|
|
||
|
|
void intel_dram_edram_detect(struct drm_i915_private *i915)
|
||
|
|
{
|
||
|
|
u32 edram_cap = 0;
|
||
|
|
|
||
|
|
if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9))
|
||
|
|
return;
|
||
|
|
|
||
|
|
edram_cap = __raw_uncore_read32(&i915->uncore, HSW_EDRAM_CAP);
|
||
|
|
|
||
|
|
/* NB: We can't write IDICR yet because we don't have gt funcs set up */
|
||
|
|
|
||
|
|
if (!(edram_cap & EDRAM_ENABLED))
|
||
|
|
return;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The needed capability bits for size calculation are not there with
|
||
|
|
* pre gen9 so return 128MB always.
|
||
|
|
*/
|
||
|
|
if (GRAPHICS_VER(i915) < 9)
|
||
|
|
i915->edram_size_mb = 128;
|
||
|
|
else
|
||
|
|
i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);
|
||
|
|
|
||
|
|
drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);
|
||
|
|
}
|