409 lines
15 KiB
C
409 lines
15 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
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*/
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#ifndef __DPU_ENCODER_PHYS_H__
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#define __DPU_ENCODER_PHYS_H__
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#include <drm/drm_writeback.h>
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#include <linux/jiffies.h>
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#include "dpu_kms.h"
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#include "dpu_hw_intf.h"
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#include "dpu_hw_wb.h"
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#include "dpu_hw_pingpong.h"
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#include "dpu_hw_ctl.h"
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#include "dpu_hw_top.h"
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#include "dpu_encoder.h"
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#include "dpu_crtc.h"
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#define DPU_ENCODER_NAME_MAX 16
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/* wait for at most 2 vsync for lowest refresh rate (24hz) */
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#define KICKOFF_TIMEOUT_MS 84
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#define KICKOFF_TIMEOUT_JIFFIES msecs_to_jiffies(KICKOFF_TIMEOUT_MS)
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/**
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* enum dpu_enc_split_role - Role this physical encoder will play in a
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* split-panel configuration, where one panel is master, and others slaves.
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* Masters have extra responsibilities, like managing the VBLANK IRQ.
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* @ENC_ROLE_SOLO: This is the one and only panel. This encoder is master.
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* @ENC_ROLE_MASTER: This encoder is the master of a split panel config.
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* @ENC_ROLE_SLAVE: This encoder is not the master of a split panel config.
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*/
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enum dpu_enc_split_role {
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ENC_ROLE_SOLO,
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ENC_ROLE_MASTER,
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ENC_ROLE_SLAVE,
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};
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/**
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* enum dpu_enc_enable_state - current enabled state of the physical encoder
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* @DPU_ENC_DISABLING: Encoder transitioning to disable state
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* Events bounding transition are encoder type specific
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* @DPU_ENC_DISABLED: Encoder is disabled
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* @DPU_ENC_ENABLING: Encoder transitioning to enabled
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* Events bounding transition are encoder type specific
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* @DPU_ENC_ENABLED: Encoder is enabled
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* @DPU_ENC_ERR_NEEDS_HW_RESET: Encoder is enabled, but requires a hw_reset
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* to recover from a previous error
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*/
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enum dpu_enc_enable_state {
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DPU_ENC_DISABLING,
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DPU_ENC_DISABLED,
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DPU_ENC_ENABLING,
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DPU_ENC_ENABLED,
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DPU_ENC_ERR_NEEDS_HW_RESET
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};
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struct dpu_encoder_phys;
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/**
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* struct dpu_encoder_phys_ops - Interface the physical encoders provide to
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* the containing virtual encoder.
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* @late_register: DRM Call. Add Userspace interfaces, debugfs.
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* @prepare_commit: MSM Atomic Call, start of atomic commit sequence
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* @is_master: Whether this phys_enc is the current master
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* encoder. Can be switched at enable time. Based
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* on split_role and current mode (CMD/VID).
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* @atomic_mode_set: DRM Call. Set a DRM mode.
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* This likely caches the mode, for use at enable.
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* @enable: DRM Call. Enable a DRM mode.
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* @disable: DRM Call. Disable mode.
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* @atomic_check: DRM Call. Atomic check new DRM state.
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* @destroy: DRM Call. Destroy and release resources.
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* @control_vblank_irq Register/Deregister for VBLANK IRQ
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* @wait_for_commit_done: Wait for hardware to have flushed the
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* current pending frames to hardware
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* @wait_for_tx_complete: Wait for hardware to transfer the pixels
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* to the panel
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* @wait_for_vblank: Wait for VBLANK, for sub-driver internal use
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* @prepare_for_kickoff: Do any work necessary prior to a kickoff
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* For CMD encoder, may wait for previous tx done
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* @handle_post_kickoff: Do any work necessary post-kickoff work
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* @trigger_start: Process start event on physical encoder
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* @needs_single_flush: Whether encoder slaves need to be flushed
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* @irq_control: Handler to enable/disable all the encoder IRQs
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* @prepare_idle_pc: phys encoder can update the vsync_enable status
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* on idle power collapse prepare
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* @restore: Restore all the encoder configs.
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* @get_line_count: Obtain current vertical line count
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*/
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struct dpu_encoder_phys_ops {
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int (*late_register)(struct dpu_encoder_phys *encoder,
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struct dentry *debugfs_root);
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void (*prepare_commit)(struct dpu_encoder_phys *encoder);
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bool (*is_master)(struct dpu_encoder_phys *encoder);
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void (*atomic_mode_set)(struct dpu_encoder_phys *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state);
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void (*enable)(struct dpu_encoder_phys *encoder);
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void (*disable)(struct dpu_encoder_phys *encoder);
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int (*atomic_check)(struct dpu_encoder_phys *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state);
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void (*destroy)(struct dpu_encoder_phys *encoder);
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int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
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int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
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int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
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int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc);
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void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
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void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
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void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
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bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
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void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
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void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
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void (*restore)(struct dpu_encoder_phys *phys);
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int (*get_line_count)(struct dpu_encoder_phys *phys);
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int (*get_frame_count)(struct dpu_encoder_phys *phys);
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void (*prepare_wb_job)(struct dpu_encoder_phys *phys_enc,
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struct drm_writeback_job *job);
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void (*cleanup_wb_job)(struct dpu_encoder_phys *phys_enc,
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struct drm_writeback_job *job);
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bool (*is_valid_for_commit)(struct dpu_encoder_phys *phys_enc);
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};
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/**
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* enum dpu_intr_idx - dpu encoder interrupt index
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* @INTR_IDX_VSYNC: Vsync interrupt for video mode panel
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* @INTR_IDX_PINGPONG: Pingpong done unterrupt for cmd mode panel
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* @INTR_IDX_UNDERRUN: Underrun unterrupt for video and cmd mode panel
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* @INTR_IDX_RDPTR: Readpointer done unterrupt for cmd mode panel
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* @INTR_IDX_WB_DONE: Writeback fone interrupt for virtual connector
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*/
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enum dpu_intr_idx {
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INTR_IDX_VSYNC,
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INTR_IDX_PINGPONG,
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INTR_IDX_UNDERRUN,
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INTR_IDX_CTL_START,
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INTR_IDX_RDPTR,
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INTR_IDX_WB_DONE,
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INTR_IDX_MAX,
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};
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/**
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* struct dpu_encoder_phys - physical encoder that drives a single INTF block
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* tied to a specific panel / sub-panel. Abstract type, sub-classed by
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* phys_vid or phys_cmd for video mode or command mode encs respectively.
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* @parent: Pointer to the containing virtual encoder
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* @ops: Operations exposed to the virtual encoder
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* @parent_ops: Callbacks exposed by the parent to the phys_enc
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* @hw_mdptop: Hardware interface to the top registers
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* @hw_ctl: Hardware interface to the ctl registers
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* @hw_pp: Hardware interface to the ping pong registers
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* @hw_intf: Hardware interface to the intf registers
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* @hw_wb: Hardware interface to the wb registers
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* @dpu_kms: Pointer to the dpu_kms top level
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* @cached_mode: DRM mode cached at mode_set time, acted on in enable
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* @enabled: Whether the encoder has enabled and running a mode
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* @split_role: Role to play in a split-panel configuration
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* @intf_mode: Interface mode
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* @intf_idx: Interface index on dpu hardware
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* @wb_idx: Writeback index on dpu hardware
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* @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
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* @enable_state: Enable state tracking
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* @vblank_refcount: Reference count of vblank request
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* @vsync_cnt: Vsync count for the physical encoder
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* @underrun_cnt: Underrun count for the physical encoder
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* @pending_kickoff_cnt: Atomic counter tracking the number of kickoffs
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* vs. the number of done/vblank irqs. Should hover
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* between 0-2 Incremented when a new kickoff is
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* scheduled. Decremented in irq handler
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* @pending_ctlstart_cnt: Atomic counter tracking the number of ctl start
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* pending.
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* @pending_kickoff_wq: Wait queue for blocking until kickoff completes
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* @irq: IRQ indices
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*/
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struct dpu_encoder_phys {
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struct drm_encoder *parent;
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struct dpu_encoder_phys_ops ops;
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struct dpu_hw_mdp *hw_mdptop;
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struct dpu_hw_ctl *hw_ctl;
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struct dpu_hw_pingpong *hw_pp;
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struct dpu_hw_intf *hw_intf;
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struct dpu_hw_wb *hw_wb;
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struct dpu_kms *dpu_kms;
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struct drm_display_mode cached_mode;
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enum dpu_enc_split_role split_role;
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enum dpu_intf_mode intf_mode;
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enum dpu_intf intf_idx;
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enum dpu_wb wb_idx;
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spinlock_t *enc_spinlock;
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enum dpu_enc_enable_state enable_state;
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atomic_t vblank_refcount;
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atomic_t vsync_cnt;
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atomic_t underrun_cnt;
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atomic_t pending_ctlstart_cnt;
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atomic_t pending_kickoff_cnt;
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wait_queue_head_t pending_kickoff_wq;
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int irq[INTR_IDX_MAX];
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};
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static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys)
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{
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atomic_inc_return(&phys->pending_ctlstart_cnt);
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return atomic_inc_return(&phys->pending_kickoff_cnt);
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}
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/**
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* struct dpu_encoder_phys_wb - sub-class of dpu_encoder_phys to handle command
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* mode specific operations
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* @base: Baseclass physical encoder structure
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* @wbirq_refcount: Reference count of writeback interrupt
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* @wb_done_timeout_cnt: number of wb done irq timeout errors
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* @wb_cfg: writeback block config to store fb related details
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* @wb_conn: backpointer to writeback connector
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* @wb_job: backpointer to current writeback job
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* @dest: dpu buffer layout for current writeback output buffer
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*/
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struct dpu_encoder_phys_wb {
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struct dpu_encoder_phys base;
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atomic_t wbirq_refcount;
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int wb_done_timeout_cnt;
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struct dpu_hw_wb_cfg wb_cfg;
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struct drm_writeback_connector *wb_conn;
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struct drm_writeback_job *wb_job;
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struct dpu_hw_fmt_layout dest;
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};
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/**
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* struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command
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* mode specific operations
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* @base: Baseclass physical encoder structure
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* @intf_idx: Intf Block index used by this phys encoder
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* @stream_sel: Stream selection for multi-stream interfaces
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* @serialize_wait4pp: serialize wait4pp feature waits for pp_done interrupt
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* after ctl_start instead of before next frame kickoff
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* @pp_timeout_report_cnt: number of pingpong done irq timeout errors
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* @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK
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* @pending_vblank_wq: Wait queue for blocking until VBLANK received
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*/
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struct dpu_encoder_phys_cmd {
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struct dpu_encoder_phys base;
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int stream_sel;
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bool serialize_wait4pp;
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int pp_timeout_report_cnt;
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atomic_t pending_vblank_cnt;
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wait_queue_head_t pending_vblank_wq;
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};
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/**
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* struct dpu_enc_phys_init_params - initialization parameters for phys encs
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* @dpu_kms: Pointer to the dpu_kms top level
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* @parent: Pointer to the containing virtual encoder
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* @parent_ops: Callbacks exposed by the parent to the phys_enc
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* @split_role: Role to play in a split-panel configuration
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* @intf_idx: Interface index this phys_enc will control
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* @wb_idx: Writeback index this phys_enc will control
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* @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
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*/
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struct dpu_enc_phys_init_params {
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struct dpu_kms *dpu_kms;
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struct drm_encoder *parent;
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enum dpu_enc_split_role split_role;
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enum dpu_intf intf_idx;
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enum dpu_wb wb_idx;
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spinlock_t *enc_spinlock;
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};
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/**
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* dpu_encoder_wait_info - container for passing arguments to irq wait functions
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* @wq: wait queue structure
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* @atomic_cnt: wait until atomic_cnt equals zero
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* @timeout_ms: timeout value in milliseconds
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*/
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struct dpu_encoder_wait_info {
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wait_queue_head_t *wq;
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atomic_t *atomic_cnt;
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s64 timeout_ms;
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};
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/**
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* dpu_encoder_phys_vid_init - Construct a new video mode physical encoder
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* @p: Pointer to init params structure
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* Return: Error code or newly allocated encoder
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*/
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struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
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struct dpu_enc_phys_init_params *p);
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/**
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* dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder
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* @p: Pointer to init params structure
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* Return: Error code or newly allocated encoder
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*/
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struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
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struct dpu_enc_phys_init_params *p);
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/**
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* dpu_encoder_phys_wb_init - initialize writeback encoder
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* @init: Pointer to init info structure with initialization params
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*/
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struct dpu_encoder_phys *dpu_encoder_phys_wb_init(
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struct dpu_enc_phys_init_params *p);
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/**
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* dpu_encoder_helper_trigger_start - control start helper function
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* This helper function may be optionally specified by physical
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* encoders if they require ctl_start triggering.
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* @phys_enc: Pointer to physical encoder structure
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*/
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void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);
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static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
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struct dpu_encoder_phys *phys_enc)
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{
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struct dpu_crtc_state *dpu_cstate;
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if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
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return BLEND_3D_NONE;
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dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
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/* Use merge_3d unless DSC MERGE topology is used */
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if (phys_enc->split_role == ENC_ROLE_SOLO &&
|
||
|
|
dpu_cstate->num_mixers == CRTC_DUAL_MIXERS &&
|
||
|
|
!dpu_encoder_use_dsc_merge(phys_enc->parent))
|
||
|
|
return BLEND_3D_H_ROW_INT;
|
||
|
|
|
||
|
|
return BLEND_3D_NONE;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
|
||
|
|
* This helper function is used by physical encoder to get DSC blocks mask
|
||
|
|
* used for this encoder.
|
||
|
|
* @phys_enc: Pointer to physical encoder structure
|
||
|
|
*/
|
||
|
|
unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* dpu_encoder_helper_split_config - split display configuration helper function
|
||
|
|
* This helper function may be used by physical encoders to configure
|
||
|
|
* the split display related registers.
|
||
|
|
* @phys_enc: Pointer to physical encoder structure
|
||
|
|
* @interface: enum dpu_intf setting
|
||
|
|
*/
|
||
|
|
void dpu_encoder_helper_split_config(
|
||
|
|
struct dpu_encoder_phys *phys_enc,
|
||
|
|
enum dpu_intf interface);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* dpu_encoder_helper_report_irq_timeout - utility to report error that irq has
|
||
|
|
* timed out, including reporting frame error event to crtc and debug dump
|
||
|
|
* @phys_enc: Pointer to physical encoder structure
|
||
|
|
* @intr_idx: Failing interrupt index
|
||
|
|
*/
|
||
|
|
void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
|
||
|
|
enum dpu_intr_idx intr_idx);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* dpu_encoder_helper_wait_for_irq - utility to wait on an irq.
|
||
|
|
* note: will call dpu_encoder_helper_wait_for_irq on timeout
|
||
|
|
* @phys_enc: Pointer to physical encoder structure
|
||
|
|
* @irq: IRQ index
|
||
|
|
* @func: IRQ callback to be called in case of timeout
|
||
|
|
* @wait_info: wait info struct
|
||
|
|
* @Return: 0 or -ERROR
|
||
|
|
*/
|
||
|
|
int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
|
||
|
|
int irq,
|
||
|
|
void (*func)(void *arg, int irq_idx),
|
||
|
|
struct dpu_encoder_wait_info *wait_info);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline
|
||
|
|
* @phys_enc: Pointer to physical encoder structure
|
||
|
|
*/
|
||
|
|
void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception
|
||
|
|
* @drm_enc: Pointer to drm encoder structure
|
||
|
|
* @phys_enc: Pointer to physical encoder
|
||
|
|
* Note: This is called from IRQ handler context.
|
||
|
|
*/
|
||
|
|
void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
|
||
|
|
struct dpu_encoder_phys *phy_enc);
|
||
|
|
|
||
|
|
/** dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception
|
||
|
|
* @drm_enc: Pointer to drm encoder structure
|
||
|
|
* @phys_enc: Pointer to physical encoder
|
||
|
|
* Note: This is called from IRQ handler context.
|
||
|
|
*/
|
||
|
|
void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
|
||
|
|
struct dpu_encoder_phys *phy_enc);
|
||
|
|
|
||
|
|
/** dpu_encoder_frame_done_callback -- Notify virtual encoder that this phys encoder completes last request frame
|
||
|
|
* @drm_enc: Pointer to drm encoder structure
|
||
|
|
* @phys_enc: Pointer to physical encoder
|
||
|
|
* @event: Event to process
|
||
|
|
*/
|
||
|
|
void dpu_encoder_frame_done_callback(
|
||
|
|
struct drm_encoder *drm_enc,
|
||
|
|
struct dpu_encoder_phys *ready_phys, u32 event);
|
||
|
|
|
||
|
|
#endif /* __dpu_encoder_phys_H__ */
|