85 lines
2.1 KiB
C
85 lines
2.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2020-2022, Linaro Limited */
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#ifndef _DPU_HW_DSC_H
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#define _DPU_HW_DSC_H
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#include <drm/display/drm_dsc.h>
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#define DSC_MODE_SPLIT_PANEL BIT(0)
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#define DSC_MODE_MULTIPLEX BIT(1)
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#define DSC_MODE_VIDEO BIT(2)
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struct dpu_hw_dsc;
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/**
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* struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
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* Assumption is these functions will be called after clocks are enabled
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*/
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struct dpu_hw_dsc_ops {
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/**
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* dsc_disable - disable dsc
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* @hw_dsc: Pointer to dsc context
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*/
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void (*dsc_disable)(struct dpu_hw_dsc *hw_dsc);
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/**
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* dsc_config - configures dsc encoder
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* @hw_dsc: Pointer to dsc context
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* @dsc: panel dsc parameters
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* @mode: dsc topology mode to be set
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* @initial_lines: amount of initial lines to be used
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*/
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void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
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struct drm_dsc_config *dsc,
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u32 mode,
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u32 initial_lines);
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/**
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* dsc_config_thresh - programs panel thresholds
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* @hw_dsc: Pointer to dsc context
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* @dsc: panel dsc parameters
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*/
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void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
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struct drm_dsc_config *dsc);
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void (*dsc_bind_pingpong_blk)(struct dpu_hw_dsc *hw_dsc,
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bool enable,
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enum dpu_pingpong pp);
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};
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struct dpu_hw_dsc {
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struct dpu_hw_blk base;
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struct dpu_hw_blk_reg_map hw;
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/* dsc */
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enum dpu_dsc idx;
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const struct dpu_dsc_cfg *caps;
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/* ops */
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struct dpu_hw_dsc_ops ops;
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};
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/**
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* dpu_hw_dsc_init - initializes the dsc block for the passed dsc idx.
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* @idx: DSC index for which driver object is required
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* @addr: Mapped register io address of MDP
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* @m: Pointer to mdss catalog data
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* Returns: Error code or allocated dpu_hw_dsc context
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*/
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struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
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const struct dpu_mdss_cfg *m);
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/**
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* dpu_hw_dsc_destroy - destroys dsc driver context
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* @dsc: Pointer to dsc driver context returned by dpu_hw_dsc_init
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*/
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void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc);
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static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw)
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{
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return container_of(hw, struct dpu_hw_dsc, base);
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}
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#endif /* _DPU_HW_DSC_H */
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