363 lines
10 KiB
C
363 lines
10 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_HW_UTIL_H
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#define _DPU_HW_UTIL_H
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "dpu_hw_mdss.h"
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#include "dpu_hw_catalog.h"
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#define REG_MASK(n) ((BIT(n)) - 1)
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#define MISR_FRAME_COUNT_MASK 0xFF
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#define MISR_CTRL_ENABLE BIT(8)
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#define MISR_CTRL_STATUS BIT(9)
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#define MISR_CTRL_STATUS_CLEAR BIT(10)
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#define MISR_CTRL_FREE_RUN_MASK BIT(31)
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/*
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* This is the common struct maintained by each sub block
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* for mapping the register offsets in this block to the
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* absoulute IO address
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* @blk_addr: hw block register mapped address
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* @log_mask: log mask for this block
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*/
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struct dpu_hw_blk_reg_map {
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void __iomem *blk_addr;
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u32 log_mask;
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};
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/**
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* struct dpu_hw_blk - opaque hardware block object
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*/
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struct dpu_hw_blk {
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/* opaque */
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};
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/**
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* struct dpu_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration
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* @enable: detail enhancer enable/disable
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* @sharpen_level1: sharpening strength for noise
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* @sharpen_level2: sharpening strength for signal
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* @ clip: clip shift
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* @ limit: limit value
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* @ thr_quiet: quiet threshold
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* @ thr_dieout: dieout threshold
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* @ thr_high: low threshold
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* @ thr_high: high threshold
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* @ prec_shift: precision shift
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* @ adjust_a: A-coefficients for mapping curve
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* @ adjust_b: B-coefficients for mapping curve
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* @ adjust_c: C-coefficients for mapping curve
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*/
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struct dpu_hw_scaler3_de_cfg {
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u32 enable;
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int16_t sharpen_level1;
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int16_t sharpen_level2;
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uint16_t clip;
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uint16_t limit;
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uint16_t thr_quiet;
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uint16_t thr_dieout;
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uint16_t thr_low;
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uint16_t thr_high;
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uint16_t prec_shift;
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int16_t adjust_a[DPU_MAX_DE_CURVES];
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int16_t adjust_b[DPU_MAX_DE_CURVES];
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int16_t adjust_c[DPU_MAX_DE_CURVES];
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};
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/**
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* struct dpu_hw_scaler3_cfg : QSEEDv3 configuration
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* @enable: scaler enable
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* @dir_en: direction detection block enable
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* @ init_phase_x: horizontal initial phase
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* @ phase_step_x: horizontal phase step
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* @ init_phase_y: vertical initial phase
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* @ phase_step_y: vertical phase step
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* @ preload_x: horizontal preload value
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* @ preload_y: vertical preload value
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* @ src_width: source width
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* @ src_height: source height
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* @ dst_width: destination width
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* @ dst_height: destination height
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* @ y_rgb_filter_cfg: y/rgb plane filter configuration
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* @ uv_filter_cfg: uv plane filter configuration
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* @ alpha_filter_cfg: alpha filter configuration
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* @ blend_cfg: blend coefficients configuration
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* @ lut_flag: scaler LUT update flags
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* 0x1 swap LUT bank
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* 0x2 update 2D filter LUT
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* 0x4 update y circular filter LUT
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* 0x8 update uv circular filter LUT
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* 0x10 update y separable filter LUT
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* 0x20 update uv separable filter LUT
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* @ dir_lut_idx: 2D filter LUT index
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* @ y_rgb_cir_lut_idx: y circular filter LUT index
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* @ uv_cir_lut_idx: uv circular filter LUT index
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* @ y_rgb_sep_lut_idx: y circular filter LUT index
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* @ uv_sep_lut_idx: uv separable filter LUT index
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* @ dir_lut: pointer to 2D LUT
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* @ cir_lut: pointer to circular filter LUT
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* @ sep_lut: pointer to separable filter LUT
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* @ de: detail enhancer configuration
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* @ dir_weight: Directional weight
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*/
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struct dpu_hw_scaler3_cfg {
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u32 enable;
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u32 dir_en;
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int32_t init_phase_x[DPU_MAX_PLANES];
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int32_t phase_step_x[DPU_MAX_PLANES];
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int32_t init_phase_y[DPU_MAX_PLANES];
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int32_t phase_step_y[DPU_MAX_PLANES];
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u32 preload_x[DPU_MAX_PLANES];
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u32 preload_y[DPU_MAX_PLANES];
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u32 src_width[DPU_MAX_PLANES];
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u32 src_height[DPU_MAX_PLANES];
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u32 dst_width;
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u32 dst_height;
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u32 y_rgb_filter_cfg;
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u32 uv_filter_cfg;
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u32 alpha_filter_cfg;
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u32 blend_cfg;
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u32 lut_flag;
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u32 dir_lut_idx;
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u32 y_rgb_cir_lut_idx;
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u32 uv_cir_lut_idx;
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u32 y_rgb_sep_lut_idx;
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u32 uv_sep_lut_idx;
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u32 *dir_lut;
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size_t dir_len;
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u32 *cir_lut;
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size_t cir_len;
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u32 *sep_lut;
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size_t sep_len;
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/*
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* Detail enhancer settings
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*/
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struct dpu_hw_scaler3_de_cfg de;
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u32 dir_weight;
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};
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/**
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* struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
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* @num_ext_pxls_lr: Number of total horizontal pixels
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* @num_ext_pxls_tb: Number of total vertical lines
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* @left_ftch: Number of extra pixels to overfetch from left
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* @right_ftch: Number of extra pixels to overfetch from right
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* @top_ftch: Number of extra lines to overfetch from top
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* @btm_ftch: Number of extra lines to overfetch from bottom
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* @left_rpt: Number of extra pixels to repeat from left
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* @right_rpt: Number of extra pixels to repeat from right
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* @top_rpt: Number of extra lines to repeat from top
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* @btm_rpt: Number of extra lines to repeat from bottom
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*/
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struct dpu_drm_pix_ext_v1 {
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/*
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* Number of pixels ext in left, right, top and bottom direction
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* for all color components.
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*/
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int32_t num_ext_pxls_lr[DPU_MAX_PLANES];
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int32_t num_ext_pxls_tb[DPU_MAX_PLANES];
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/*
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* Number of pixels needs to be overfetched in left, right, top
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* and bottom directions from source image for scaling.
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*/
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int32_t left_ftch[DPU_MAX_PLANES];
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int32_t right_ftch[DPU_MAX_PLANES];
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int32_t top_ftch[DPU_MAX_PLANES];
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int32_t btm_ftch[DPU_MAX_PLANES];
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/*
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* Number of pixels needs to be repeated in left, right, top and
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* bottom directions for scaling.
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*/
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int32_t left_rpt[DPU_MAX_PLANES];
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int32_t right_rpt[DPU_MAX_PLANES];
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int32_t top_rpt[DPU_MAX_PLANES];
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int32_t btm_rpt[DPU_MAX_PLANES];
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};
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/**
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* struct dpu_drm_de_v1 - version 1 of detail enhancer structure
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* @enable: Enables/disables detail enhancer
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* @sharpen_level1: Sharpening strength for noise
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* @sharpen_level2: Sharpening strength for context
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* @clip: Clip coefficient
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* @limit: Detail enhancer limit factor
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* @thr_quiet: Quite zone threshold
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* @thr_dieout: Die-out zone threshold
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* @thr_low: Linear zone left threshold
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* @thr_high: Linear zone right threshold
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* @prec_shift: Detail enhancer precision
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* @adjust_a: Mapping curves A coefficients
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* @adjust_b: Mapping curves B coefficients
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* @adjust_c: Mapping curves C coefficients
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*/
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struct dpu_drm_de_v1 {
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uint32_t enable;
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int16_t sharpen_level1;
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int16_t sharpen_level2;
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uint16_t clip;
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uint16_t limit;
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uint16_t thr_quiet;
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uint16_t thr_dieout;
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uint16_t thr_low;
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uint16_t thr_high;
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uint16_t prec_shift;
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int16_t adjust_a[DPU_MAX_DE_CURVES];
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int16_t adjust_b[DPU_MAX_DE_CURVES];
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int16_t adjust_c[DPU_MAX_DE_CURVES];
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};
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/**
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* struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler
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* @enable: Scaler enable
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* @dir_en: Detail enhancer enable
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* @pe: Pixel extension settings
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* @horz_decimate: Horizontal decimation factor
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* @vert_decimate: Vertical decimation factor
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* @init_phase_x: Initial scaler phase values for x
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* @phase_step_x: Phase step values for x
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* @init_phase_y: Initial scaler phase values for y
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* @phase_step_y: Phase step values for y
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* @preload_x: Horizontal preload value
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* @preload_y: Vertical preload value
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* @src_width: Source width
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* @src_height: Source height
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* @dst_width: Destination width
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* @dst_height: Destination height
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* @y_rgb_filter_cfg: Y/RGB plane filter configuration
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* @uv_filter_cfg: UV plane filter configuration
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* @alpha_filter_cfg: Alpha filter configuration
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* @blend_cfg: Selection of blend coefficients
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* @lut_flag: LUT configuration flags
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* @dir_lut_idx: 2d 4x4 LUT index
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* @y_rgb_cir_lut_idx: Y/RGB circular LUT index
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* @uv_cir_lut_idx: UV circular LUT index
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* @y_rgb_sep_lut_idx: Y/RGB separable LUT index
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* @uv_sep_lut_idx: UV separable LUT index
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* @de: Detail enhancer settings
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*/
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struct dpu_drm_scaler_v2 {
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/*
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* General definitions
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*/
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uint32_t enable;
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uint32_t dir_en;
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/*
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* Pix ext settings
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*/
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struct dpu_drm_pix_ext_v1 pe;
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/*
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* Decimation settings
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*/
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uint32_t horz_decimate;
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uint32_t vert_decimate;
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/*
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* Phase settings
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*/
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int32_t init_phase_x[DPU_MAX_PLANES];
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int32_t phase_step_x[DPU_MAX_PLANES];
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int32_t init_phase_y[DPU_MAX_PLANES];
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int32_t phase_step_y[DPU_MAX_PLANES];
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uint32_t preload_x[DPU_MAX_PLANES];
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uint32_t preload_y[DPU_MAX_PLANES];
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uint32_t src_width[DPU_MAX_PLANES];
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uint32_t src_height[DPU_MAX_PLANES];
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uint32_t dst_width;
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uint32_t dst_height;
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uint32_t y_rgb_filter_cfg;
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uint32_t uv_filter_cfg;
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uint32_t alpha_filter_cfg;
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uint32_t blend_cfg;
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uint32_t lut_flag;
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uint32_t dir_lut_idx;
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/* for Y(RGB) and UV planes*/
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uint32_t y_rgb_cir_lut_idx;
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uint32_t uv_cir_lut_idx;
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uint32_t y_rgb_sep_lut_idx;
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uint32_t uv_sep_lut_idx;
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/*
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* Detail enhancer settings
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*/
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struct dpu_drm_de_v1 de;
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};
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/**
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* struct dpu_hw_cdp_cfg : CDP configuration
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* @enable: true to enable CDP
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* @ubwc_meta_enable: true to enable ubwc metadata preload
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* @tile_amortize_enable: true to enable amortization control for tile format
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* @preload_ahead: number of request to preload ahead
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* DPU_*_CDP_PRELOAD_AHEAD_32,
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* DPU_*_CDP_PRELOAD_AHEAD_64
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*/
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struct dpu_hw_cdp_cfg {
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bool enable;
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bool ubwc_meta_enable;
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bool tile_amortize_enable;
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u32 preload_ahead;
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};
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u32 *dpu_hw_util_get_log_mask_ptr(void);
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void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
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u32 reg_off,
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u32 val,
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const char *name);
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int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off);
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#define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off)
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#define DPU_REG_READ(c, off) dpu_reg_read(c, off)
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void *dpu_hw_util_get_dir(void);
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void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
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struct dpu_hw_scaler3_cfg *scaler3_cfg,
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u32 scaler_offset, u32 scaler_version,
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const struct dpu_format *format);
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u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c,
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u32 scaler_offset);
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void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
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u32 csc_reg_off,
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const struct dpu_csc_cfg *data, bool csc10);
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u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
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u32 total_fl);
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void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
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u32 misr_ctrl_offset,
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bool enable,
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u32 frame_count);
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int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
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u32 misr_ctrl_offset,
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u32 misr_signature_offset,
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u32 *misr_value);
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#endif /* _DPU_HW_UTIL_H */
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