278 lines
7.8 KiB
C
278 lines
7.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved
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*/
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#include "dpu_hw_mdss.h"
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#include "dpu_hwio.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_wb.h"
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#include "dpu_formats.h"
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#include "dpu_kms.h"
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#define WB_DST_FORMAT 0x000
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#define WB_DST_OP_MODE 0x004
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#define WB_DST_PACK_PATTERN 0x008
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#define WB_DST0_ADDR 0x00C
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#define WB_DST1_ADDR 0x010
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#define WB_DST2_ADDR 0x014
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#define WB_DST3_ADDR 0x018
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#define WB_DST_YSTRIDE0 0x01C
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#define WB_DST_YSTRIDE1 0x020
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#define WB_DST_YSTRIDE1 0x020
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#define WB_DST_DITHER_BITDEPTH 0x024
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#define WB_DST_MATRIX_ROW0 0x030
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#define WB_DST_MATRIX_ROW1 0x034
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#define WB_DST_MATRIX_ROW2 0x038
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#define WB_DST_MATRIX_ROW3 0x03C
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#define WB_DST_WRITE_CONFIG 0x048
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#define WB_ROTATION_DNSCALER 0x050
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#define WB_ROTATOR_PIPE_DOWNSCALER 0x054
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#define WB_N16_INIT_PHASE_X_C03 0x060
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#define WB_N16_INIT_PHASE_X_C12 0x064
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#define WB_N16_INIT_PHASE_Y_C03 0x068
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#define WB_N16_INIT_PHASE_Y_C12 0x06C
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#define WB_OUT_SIZE 0x074
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#define WB_ALPHA_X_VALUE 0x078
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#define WB_DANGER_LUT 0x084
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#define WB_SAFE_LUT 0x088
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#define WB_QOS_CTRL 0x090
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#define WB_CREQ_LUT_0 0x098
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#define WB_CREQ_LUT_1 0x09C
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#define WB_UBWC_STATIC_CTRL 0x144
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#define WB_MUX 0x150
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#define WB_CROP_CTRL 0x154
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#define WB_CROP_OFFSET 0x158
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#define WB_CSC_BASE 0x260
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#define WB_DST_ADDR_SW_STATUS 0x2B0
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#define WB_CDP_CNTL 0x2B4
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#define WB_OUT_IMAGE_SIZE 0x2C0
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#define WB_OUT_XY 0x2C4
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/* WB_QOS_CTRL */
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#define WB_QOS_CTRL_DANGER_SAFE_EN BIT(0)
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static const struct dpu_wb_cfg *_wb_offset(enum dpu_wb wb,
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const struct dpu_mdss_cfg *m, void __iomem *addr,
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struct dpu_hw_blk_reg_map *b)
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{
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int i;
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for (i = 0; i < m->wb_count; i++) {
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if (wb == m->wb[i].id) {
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b->blk_addr = addr + m->wb[i].base;
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b->log_mask = DPU_DBG_MASK_WB;
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return &m->wb[i];
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}
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}
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return ERR_PTR(-EINVAL);
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}
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static void dpu_hw_wb_setup_outaddress(struct dpu_hw_wb *ctx,
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struct dpu_hw_wb_cfg *data)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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DPU_REG_WRITE(c, WB_DST0_ADDR, data->dest.plane_addr[0]);
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DPU_REG_WRITE(c, WB_DST1_ADDR, data->dest.plane_addr[1]);
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DPU_REG_WRITE(c, WB_DST2_ADDR, data->dest.plane_addr[2]);
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DPU_REG_WRITE(c, WB_DST3_ADDR, data->dest.plane_addr[3]);
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}
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static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
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struct dpu_hw_wb_cfg *data)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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const struct dpu_format *fmt = data->dest.format;
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u32 dst_format, pattern, ystride0, ystride1, outsize, chroma_samp;
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u32 write_config = 0;
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u32 opmode = 0;
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u32 dst_addr_sw = 0;
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chroma_samp = fmt->chroma_sample;
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dst_format = (chroma_samp << 23) |
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(fmt->fetch_planes << 19) |
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(fmt->bits[C3_ALPHA] << 6) |
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(fmt->bits[C2_R_Cr] << 4) |
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(fmt->bits[C1_B_Cb] << 2) |
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(fmt->bits[C0_G_Y] << 0);
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if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) {
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dst_format |= BIT(8); /* DSTC3_EN */
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if (!fmt->alpha_enable ||
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!(ctx->caps->features & BIT(DPU_WB_PIPE_ALPHA)))
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dst_format |= BIT(14); /* DST_ALPHA_X */
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}
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pattern = (fmt->element[3] << 24) |
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(fmt->element[2] << 16) |
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(fmt->element[1] << 8) |
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(fmt->element[0] << 0);
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dst_format |= (fmt->unpack_align_msb << 18) |
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(fmt->unpack_tight << 17) |
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((fmt->unpack_count - 1) << 12) |
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((fmt->bpp - 1) << 9);
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ystride0 = data->dest.plane_pitch[0] |
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(data->dest.plane_pitch[1] << 16);
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ystride1 = data->dest.plane_pitch[2] |
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(data->dest.plane_pitch[3] << 16);
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if (drm_rect_height(&data->roi) && drm_rect_width(&data->roi))
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outsize = (drm_rect_height(&data->roi) << 16) | drm_rect_width(&data->roi);
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else
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outsize = (data->dest.height << 16) | data->dest.width;
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DPU_REG_WRITE(c, WB_ALPHA_X_VALUE, 0xFF);
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DPU_REG_WRITE(c, WB_DST_FORMAT, dst_format);
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DPU_REG_WRITE(c, WB_DST_OP_MODE, opmode);
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DPU_REG_WRITE(c, WB_DST_PACK_PATTERN, pattern);
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DPU_REG_WRITE(c, WB_DST_YSTRIDE0, ystride0);
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DPU_REG_WRITE(c, WB_DST_YSTRIDE1, ystride1);
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DPU_REG_WRITE(c, WB_OUT_SIZE, outsize);
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DPU_REG_WRITE(c, WB_DST_WRITE_CONFIG, write_config);
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DPU_REG_WRITE(c, WB_DST_ADDR_SW_STATUS, dst_addr_sw);
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}
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static void dpu_hw_wb_roi(struct dpu_hw_wb *ctx, struct dpu_hw_wb_cfg *wb)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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u32 image_size, out_size, out_xy;
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image_size = (wb->dest.height << 16) | wb->dest.width;
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out_xy = 0;
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out_size = (drm_rect_height(&wb->roi) << 16) | drm_rect_width(&wb->roi);
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DPU_REG_WRITE(c, WB_OUT_IMAGE_SIZE, image_size);
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DPU_REG_WRITE(c, WB_OUT_XY, out_xy);
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DPU_REG_WRITE(c, WB_OUT_SIZE, out_size);
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}
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static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx,
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struct dpu_hw_wb_qos_cfg *cfg)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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u32 qos_ctrl = 0;
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if (!ctx || !cfg)
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return;
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DPU_REG_WRITE(c, WB_DANGER_LUT, cfg->danger_lut);
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DPU_REG_WRITE(c, WB_SAFE_LUT, cfg->safe_lut);
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/*
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* for chipsets not using DPU_WB_QOS_8LVL but still using DPU
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* driver such as msm8998, the reset value of WB_CREQ_LUT is
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* sufficient for writeback to work. SW doesn't need to explicitly
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* program a value.
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*/
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if (ctx->caps && test_bit(DPU_WB_QOS_8LVL, &ctx->caps->features)) {
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DPU_REG_WRITE(c, WB_CREQ_LUT_0, cfg->creq_lut);
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DPU_REG_WRITE(c, WB_CREQ_LUT_1, cfg->creq_lut >> 32);
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}
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if (cfg->danger_safe_en)
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qos_ctrl |= WB_QOS_CTRL_DANGER_SAFE_EN;
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DPU_REG_WRITE(c, WB_QOS_CTRL, qos_ctrl);
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}
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static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
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struct dpu_hw_cdp_cfg *cfg)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 cdp_cntl = 0;
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if (!ctx || !cfg)
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return;
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c = &ctx->hw;
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if (cfg->enable)
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cdp_cntl |= BIT(0);
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if (cfg->ubwc_meta_enable)
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cdp_cntl |= BIT(1);
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if (cfg->preload_ahead == DPU_WB_CDP_PRELOAD_AHEAD_64)
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cdp_cntl |= BIT(3);
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DPU_REG_WRITE(c, WB_CDP_CNTL, cdp_cntl);
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}
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static void dpu_hw_wb_bind_pingpong_blk(
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struct dpu_hw_wb *ctx,
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bool enable, const enum dpu_pingpong pp)
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{
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struct dpu_hw_blk_reg_map *c;
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int mux_cfg;
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if (!ctx)
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return;
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c = &ctx->hw;
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mux_cfg = DPU_REG_READ(c, WB_MUX);
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mux_cfg &= ~0xf;
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if (enable)
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mux_cfg |= (pp - PINGPONG_0) & 0x7;
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else
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mux_cfg |= 0xf;
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DPU_REG_WRITE(c, WB_MUX, mux_cfg);
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}
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static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,
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unsigned long features)
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{
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ops->setup_outaddress = dpu_hw_wb_setup_outaddress;
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ops->setup_outformat = dpu_hw_wb_setup_format;
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if (test_bit(DPU_WB_XY_ROI_OFFSET, &features))
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ops->setup_roi = dpu_hw_wb_roi;
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if (test_bit(DPU_WB_QOS, &features))
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ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
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if (test_bit(DPU_WB_CDP, &features))
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ops->setup_cdp = dpu_hw_wb_setup_cdp;
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if (test_bit(DPU_WB_INPUT_CTRL, &features))
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ops->bind_pingpong_blk = dpu_hw_wb_bind_pingpong_blk;
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}
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struct dpu_hw_wb *dpu_hw_wb_init(enum dpu_wb idx,
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void __iomem *addr, const struct dpu_mdss_cfg *m)
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{
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struct dpu_hw_wb *c;
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const struct dpu_wb_cfg *cfg;
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if (!addr || !m)
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return ERR_PTR(-EINVAL);
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c = kzalloc(sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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cfg = _wb_offset(idx, m, addr, &c->hw);
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if (IS_ERR(cfg)) {
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WARN(1, "Unable to find wb idx=%d\n", idx);
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kfree(c);
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return ERR_PTR(-EINVAL);
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}
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/* Assign ops */
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c->mdp = &m->mdp[0];
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c->idx = idx;
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c->caps = cfg;
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_setup_wb_ops(&c->ops, c->caps->features);
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return c;
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}
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void dpu_hw_wb_destroy(struct dpu_hw_wb *hw_wb)
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{
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kfree(hw_wb);
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}
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