244 lines
7.6 KiB
C
244 lines
7.6 KiB
C
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/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "wndw.h"
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#include "atom.h"
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#include <drm/drm_atomic_helper.h>
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#include <nouveau_bo.h>
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#include <nvif/pushc37b.h>
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#include <nvhw/class/clc57e.h>
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static int
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wndwc57e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
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{
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struct nvif_push *push = wndw->wndw.push;
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int ret;
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if ((ret = PUSH_WAIT(push, 17)))
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return ret;
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PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
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NVVAL(NVC57E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval) |
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NVVAL(NVC57E, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) |
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NVDEF(NVC57E, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE));
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PUSH_MTHD(push, NVC57E, SET_SIZE,
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NVVAL(NVC57E, SET_SIZE, WIDTH, asyw->image.w) |
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NVVAL(NVC57E, SET_SIZE, HEIGHT, asyw->image.h),
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SET_STORAGE,
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NVVAL(NVC57E, SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |
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NVVAL(NVC57E, SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),
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SET_PARAMS,
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NVVAL(NVC57E, SET_PARAMS, FORMAT, asyw->image.format) |
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NVDEF(NVC57E, SET_PARAMS, CLAMP_BEFORE_BLEND, DISABLE) |
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NVDEF(NVC57E, SET_PARAMS, SWAP_UV, DISABLE) |
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NVDEF(NVC57E, SET_PARAMS, FMT_ROUNDING_MODE, ROUND_TO_NEAREST),
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SET_PLANAR_STORAGE(0),
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NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.blocks[0]) |
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NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.pitch[0] >> 6));
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PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
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PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
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PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
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NVVAL(NVC57E, SET_POINT_IN, X, asyw->state.src_x >> 16) |
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NVVAL(NVC57E, SET_POINT_IN, Y, asyw->state.src_y >> 16));
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PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
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NVVAL(NVC57E, SET_SIZE_IN, WIDTH, asyw->state.src_w >> 16) |
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NVVAL(NVC57E, SET_SIZE_IN, HEIGHT, asyw->state.src_h >> 16));
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PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
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NVVAL(NVC57E, SET_SIZE_OUT, WIDTH, asyw->state.crtc_w) |
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NVVAL(NVC57E, SET_SIZE_OUT, HEIGHT, asyw->state.crtc_h));
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return 0;
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}
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int
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wndwc57e_csc_clr(struct nv50_wndw *wndw)
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{
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struct nvif_push *push = wndw->wndw.push;
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const u32 identity[12] = {
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0x00010000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000, 0x00010000, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00010000, 0x00000000,
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};
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int ret;
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if ((ret = PUSH_WAIT(push, 1 + ARRAY_SIZE(identity))))
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return ret;
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PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, identity, ARRAY_SIZE(identity));
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return 0;
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}
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int
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wndwc57e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
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{
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struct nvif_push *push = wndw->wndw.push;
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int ret;
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if ((ret = PUSH_WAIT(push, 13)))
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return ret;
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PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, asyw->csc.matrix, 12);
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return 0;
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}
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int
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wndwc57e_ilut_clr(struct nv50_wndw *wndw)
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{
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struct nvif_push *push = wndw->wndw.push;
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int ret;
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if ((ret = PUSH_WAIT(push, 2)))
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return ret;
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PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ILUT, 0x00000000);
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return 0;
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}
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int
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wndwc57e_ilut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
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{
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struct nvif_push *push = wndw->wndw.push;
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int ret;
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if ((ret = PUSH_WAIT(push, 4)))
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return ret;
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PUSH_MTHD(push, NVC57E, SET_ILUT_CONTROL,
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NVVAL(NVC57E, SET_ILUT_CONTROL, SIZE, asyw->xlut.i.size) |
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NVVAL(NVC57E, SET_ILUT_CONTROL, MODE, asyw->xlut.i.mode) |
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NVVAL(NVC57E, SET_ILUT_CONTROL, INTERPOLATE, asyw->xlut.i.output_mode),
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SET_CONTEXT_DMA_ILUT, asyw->xlut.handle,
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SET_OFFSET_ILUT, asyw->xlut.i.offset >> 8);
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return 0;
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}
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static u16
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fixedU0_16_FP16(u16 fixed)
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{
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int sign = 0, exp = 0, man = 0;
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if (fixed) {
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while (--exp && !(fixed & 0x8000))
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fixed <<= 1;
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man = ((fixed << 1) & 0xffc0) >> 6;
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exp += 15;
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}
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return (sign << 15) | (exp << 10) | man;
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}
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static void
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wndwc57e_ilut_load(struct drm_color_lut *in, int size, void __iomem *mem)
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{
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memset_io(mem, 0x00, 0x20); /* VSS header. */
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mem += 0x20;
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for (; size--; in++, mem += 0x08) {
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u16 r = fixedU0_16_FP16(drm_color_lut_extract(in-> red, 16));
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u16 g = fixedU0_16_FP16(drm_color_lut_extract(in->green, 16));
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u16 b = fixedU0_16_FP16(drm_color_lut_extract(in-> blue, 16));
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writew(r, mem + 0);
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writew(g, mem + 2);
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writew(b, mem + 4);
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}
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/* INTERPOLATE modes require a "next" entry to interpolate with,
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* so we replicate the last entry to deal with this for now.
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*/
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writew(readw(mem - 8), mem + 0);
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writew(readw(mem - 6), mem + 2);
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writew(readw(mem - 4), mem + 4);
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}
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void
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wndwc57e_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, int size)
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{
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if (!size)
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size = 1024;
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if (size == 256)
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asyw->xlut.i.mode = NVC57E_SET_ILUT_CONTROL_MODE_DIRECT8;
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else
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asyw->xlut.i.mode = NVC57E_SET_ILUT_CONTROL_MODE_DIRECT10;
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asyw->xlut.i.size = 4 /* VSS header. */ + size + 1 /* Entries. */;
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asyw->xlut.i.output_mode = NVC57E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE;
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asyw->xlut.i.load = wndwc57e_ilut_load;
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}
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/****************************************************************
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* Log2(block height) ----------------------------+ *
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* Page Kind ----------------------------------+ | *
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* Gob Height/Page Kind Generation ------+ | | *
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* Sector layout -------+ | | | *
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* Compression ------+ | | | | */
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const u64 wndwc57e_modifiers[] = { /* | | | | | */
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 0),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 1),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 2),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 3),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 4),
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 5),
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DRM_FORMAT_MOD_LINEAR,
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DRM_FORMAT_MOD_INVALID
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};
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static const struct nv50_wndw_func
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wndwc57e = {
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.acquire = wndwc37e_acquire,
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.release = wndwc37e_release,
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.sema_set = wndwc37e_sema_set,
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.sema_clr = wndwc37e_sema_clr,
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.ntfy_set = wndwc37e_ntfy_set,
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.ntfy_clr = wndwc37e_ntfy_clr,
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.ntfy_reset = corec37d_ntfy_init,
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.ntfy_wait_begun = base507c_ntfy_wait_begun,
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.ilut = wndwc57e_ilut,
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.ilut_identity = true,
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.ilut_size = 1024,
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.xlut_set = wndwc57e_ilut_set,
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.xlut_clr = wndwc57e_ilut_clr,
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.csc = base907c_csc,
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.csc_set = wndwc57e_csc_set,
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.csc_clr = wndwc57e_csc_clr,
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.image_set = wndwc57e_image_set,
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.image_clr = wndwc37e_image_clr,
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.blend_set = wndwc37e_blend_set,
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.update = wndwc37e_update,
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};
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int
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wndwc57e_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
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s32 oclass, struct nv50_wndw **pwndw)
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{
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return wndwc37e_new_(&wndwc57e, drm, type, index, oclass,
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BIT(index >> 1), pwndw);
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}
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