237 lines
7.1 KiB
C
237 lines
7.1 KiB
C
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/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "chan.h"
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#include "priv.h"
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#include "head.h"
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#include "ior.h"
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#include <core/gpuobj.h>
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#include <subdev/timer.h>
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#include <nvif/class.h>
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void
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tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head, u8 slot, u8 slot_nr, u16 pbn, u16 aligned)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 hoff = head * 0x800;
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nvkm_mask(device, 0x61657c + hoff, 0xffffffff, (aligned << 16) | pbn);
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nvkm_mask(device, 0x616578 + hoff, 0x00003f3f, (slot_nr << 8) | slot);
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}
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static int
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tu102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 soff = nv50_ior_base(sor);
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const u32 loff = nv50_sor_link(sor);
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u32 dpctrl = 0x00000000;
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u32 clksor = 0x00000000;
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clksor |= sor->dp.bw << 18;
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dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
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if (sor->dp.mst)
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dpctrl |= 0x40000000;
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if (sor->dp.ef)
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dpctrl |= 0x00004000;
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nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
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/*XXX*/
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nvkm_msec(device, 40, NVKM_DELAY);
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nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000);
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nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001);
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nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
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return 0;
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}
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static const struct nvkm_ior_func_dp
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tu102_sor_dp = {
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.lanes = { 0, 1, 2, 3 },
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.links = tu102_sor_dp_links,
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.power = g94_sor_dp_power,
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.pattern = gm107_sor_dp_pattern,
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.drive = gm200_sor_dp_drive,
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.vcpi = tu102_sor_dp_vcpi,
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.audio = gv100_sor_dp_audio,
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.audio_sym = gv100_sor_dp_audio_sym,
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.watermark = gv100_sor_dp_watermark,
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};
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static const struct nvkm_ior_func
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tu102_sor = {
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.route = {
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.get = gm200_sor_route_get,
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.set = gm200_sor_route_set,
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},
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.state = gv100_sor_state,
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.power = nv50_sor_power,
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.clock = gf119_sor_clock,
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.hdmi = &gv100_sor_hdmi,
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.dp = &tu102_sor_dp,
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.hda = &gv100_sor_hda,
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};
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static int
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tu102_sor_new(struct nvkm_disp *disp, int id)
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{
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struct nvkm_device *device = disp->engine.subdev.device;
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u32 hda = nvkm_rd32(device, 0x08a15c);
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return nvkm_ior_new_(&tu102_sor, disp, SOR, id, hda & BIT(id));
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}
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int
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tu102_disp_init(struct nvkm_disp *disp)
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{
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struct nvkm_device *device = disp->engine.subdev.device;
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struct nvkm_head *head;
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int i, j;
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u32 tmp;
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/* Claim ownership of display. */
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if (nvkm_rd32(device, 0x6254e8) & 0x00000002) {
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nvkm_mask(device, 0x6254e8, 0x00000001, 0x00000000);
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if (nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002))
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break;
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) < 0)
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return -EBUSY;
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}
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/* Lock pin capabilities. */
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tmp = 0x00000021; /*XXX*/
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nvkm_wr32(device, 0x640008, tmp);
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/* SOR capabilities. */
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for (i = 0; i < disp->sor.nr; i++) {
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tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
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nvkm_mask(device, 0x640000, 0x00000100 << i, 0x00000100 << i);
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nvkm_wr32(device, 0x640144 + (i * 0x08), tmp);
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}
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/* Head capabilities. */
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list_for_each_entry(head, &disp->heads, head) {
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const int id = head->id;
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/* RG. */
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tmp = nvkm_rd32(device, 0x616300 + (id * 0x800));
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nvkm_wr32(device, 0x640048 + (id * 0x020), tmp);
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/* POSTCOMP. */
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for (j = 0; j < 5 * 4; j += 4) {
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tmp = nvkm_rd32(device, 0x616140 + (id * 0x800) + j);
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nvkm_wr32(device, 0x640680 + (id * 0x20) + j, tmp);
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}
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}
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/* Window capabilities. */
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for (i = 0; i < disp->wndw.nr; i++) {
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nvkm_mask(device, 0x640004, 1 << i, 1 << i);
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for (j = 0; j < 6 * 4; j += 4) {
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tmp = nvkm_rd32(device, 0x630100 + (i * 0x800) + j);
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nvkm_mask(device, 0x640780 + (i * 0x20) + j, 0xffffffff, tmp);
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}
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nvkm_mask(device, 0x64000c, 0x00000100, 0x00000100);
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}
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/* IHUB capabilities. */
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for (i = 0; i < 3; i++) {
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tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04));
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nvkm_wr32(device, 0x640010 + (i * 0x04), tmp);
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}
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nvkm_mask(device, 0x610078, 0x00000001, 0x00000001);
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/* Setup instance memory. */
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switch (nvkm_memory_target(disp->inst->memory)) {
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case NVKM_MEM_TARGET_VRAM: tmp = 0x00000001; break;
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case NVKM_MEM_TARGET_NCOH: tmp = 0x00000002; break;
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case NVKM_MEM_TARGET_HOST: tmp = 0x00000003; break;
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default:
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break;
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}
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nvkm_wr32(device, 0x610010, 0x00000008 | tmp);
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nvkm_wr32(device, 0x610014, disp->inst->addr >> 16);
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/* CTRL_DISP: AWAKEN, ERROR, SUPERVISOR[1-3]. */
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nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */
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nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */
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/* EXC_OTHER: CURSn, CORE. */
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nvkm_wr32(device, 0x611cec, disp->head.mask << 16 |
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0x00000001); /* MSK. */
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nvkm_wr32(device, 0x611dac, 0x00000000); /* EN. */
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/* EXC_WINIM. */
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nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */
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nvkm_wr32(device, 0x611da8, 0x00000000); /* EN. */
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/* EXC_WIN. */
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nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */
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nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */
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/* HEAD_TIMING(n): VBLANK. */
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list_for_each_entry(head, &disp->heads, head) {
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const u32 hoff = head->id * 4;
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nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */
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nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */
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}
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/* OR. */
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nvkm_wr32(device, 0x611cf4, 0x00000000); /* MSK. */
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nvkm_wr32(device, 0x611db4, 0x00000000); /* EN. */
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return 0;
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}
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static const struct nvkm_disp_func
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tu102_disp = {
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.oneinit = nv50_disp_oneinit,
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.init = tu102_disp_init,
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.fini = gv100_disp_fini,
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.intr = gv100_disp_intr,
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.super = gv100_disp_super,
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.uevent = &gv100_disp_chan_uevent,
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.wndw = { .cnt = gv100_disp_wndw_cnt },
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.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
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.sor = { .cnt = gv100_sor_cnt, .new = tu102_sor_new },
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.ramht_size = 0x2000,
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.root = { 0, 0,TU102_DISP },
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.user = {
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{{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new },
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{{ 0, 0,TU102_DISP_CURSOR }, nvkm_disp_chan_new, &gv100_disp_curs },
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{{ 0, 0,TU102_DISP_WINDOW_IMM_CHANNEL_DMA}, nvkm_disp_wndw_new, &gv100_disp_wimm },
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{{ 0, 0,TU102_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, &gv100_disp_core },
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{{ 0, 0,TU102_DISP_WINDOW_CHANNEL_DMA }, nvkm_disp_wndw_new, &gv100_disp_wndw },
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{}
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},
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};
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int
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tu102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_disp **pdisp)
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{
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return nvkm_disp_new_(&tu102_disp, device, type, inst, pdisp);
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}
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