232 lines
7.0 KiB
C
232 lines
7.0 KiB
C
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "priv.h"
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#include "cgrp.h"
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#include "chan.h"
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#include "runl.h"
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#include <core/ramht.h>
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#include <subdev/timer.h>
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#include <nvif/class.h>
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static void
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g84_chan_bind(struct nvkm_chan *chan)
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{
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struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device;
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nvkm_wr32(device, 0x002600 + (chan->id * 4), chan->ramfc->addr >> 8);
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}
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static int
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g84_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv)
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{
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struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device;
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const u32 limit2 = ilog2(length / 8);
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int ret;
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ret = nvkm_gpuobj_new(device, 0x0200, 0, true, chan->inst, &chan->eng);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, 0x4000, 0, false, chan->inst, &chan->pgd);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, 0x1000, 0x400, true, chan->inst, &chan->cache);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, chan->inst, &chan->ramfc);
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if (ret)
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return ret;
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ret = nvkm_ramht_new(device, 0x8000, 16, chan->inst, &chan->ramht);
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if (ret)
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return ret;
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nvkm_kmap(chan->ramfc);
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nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078);
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nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
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nvkm_wo32(chan->ramfc, 0x48, chan->push->node->offset >> 4);
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nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(offset));
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nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(offset) | (limit2 << 16));
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nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
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nvkm_wo32(chan->ramfc, 0x78, 0x00000000);
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nvkm_wo32(chan->ramfc, 0x7c, 0x30000000 | devm);
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nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
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(4 << 24) /* SEARCH_FULL */ |
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(chan->ramht->gpuobj->node->offset >> 4));
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nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10);
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nvkm_wo32(chan->ramfc, 0x98, chan->inst->addr >> 12);
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nvkm_done(chan->ramfc);
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return 0;
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}
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static const struct nvkm_chan_func_ramfc
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g84_chan_ramfc = {
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.write = g84_chan_ramfc_write,
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.ctxdma = true,
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.devm = 0xfff,
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};
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const struct nvkm_chan_func
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g84_chan = {
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.inst = &nv50_chan_inst,
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.userd = &nv50_chan_userd,
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.ramfc = &g84_chan_ramfc,
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.bind = g84_chan_bind,
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.unbind = nv50_chan_unbind,
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.start = nv50_chan_start,
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.stop = nv50_chan_stop,
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};
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static void
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g84_ectx_bind(struct nvkm_engn *engn, struct nvkm_cctx *cctx, struct nvkm_chan *chan)
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{
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struct nvkm_subdev *subdev = &chan->cgrp->runl->fifo->engine.subdev;
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struct nvkm_device *device = subdev->device;
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u64 start = 0, limit = 0;
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u32 flags = 0, ptr0, save;
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switch (engn->engine->subdev.type) {
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case NVKM_ENGINE_GR : ptr0 = 0x0020; break;
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case NVKM_ENGINE_VP :
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case NVKM_ENGINE_MSPDEC: ptr0 = 0x0040; break;
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case NVKM_ENGINE_MPEG :
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case NVKM_ENGINE_MSPPP : ptr0 = 0x0060; break;
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case NVKM_ENGINE_BSP :
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case NVKM_ENGINE_MSVLD : ptr0 = 0x0080; break;
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case NVKM_ENGINE_CIPHER:
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case NVKM_ENGINE_SEC : ptr0 = 0x00a0; break;
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case NVKM_ENGINE_CE : ptr0 = 0x00c0; break;
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default:
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WARN_ON(1);
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return;
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}
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if (!cctx) {
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save = nvkm_mask(device, 0x002520, 0x0000003f, BIT(engn->id - 1));
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nvkm_wr32(device, 0x0032fc, chan->inst->addr >> 12);
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nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x0032fc) != 0xffffffff)
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break;
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);
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nvkm_wr32(device, 0x002520, save);
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} else {
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flags = 0x00190000;
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start = cctx->vctx->inst->addr;
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limit = start + cctx->vctx->inst->size - 1;
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}
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nvkm_kmap(chan->eng);
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nvkm_wo32(chan->eng, ptr0 + 0x00, flags);
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nvkm_wo32(chan->eng, ptr0 + 0x04, lower_32_bits(limit));
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nvkm_wo32(chan->eng, ptr0 + 0x08, lower_32_bits(start));
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nvkm_wo32(chan->eng, ptr0 + 0x0c, upper_32_bits(limit) << 24 |
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lower_32_bits(start));
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nvkm_wo32(chan->eng, ptr0 + 0x10, 0x00000000);
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nvkm_wo32(chan->eng, ptr0 + 0x14, 0x00000000);
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nvkm_done(chan->eng);
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}
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const struct nvkm_engn_func
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g84_engn = {
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.bind = g84_ectx_bind,
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.ramht_add = nv50_eobj_ramht_add,
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.ramht_del = nv50_eobj_ramht_del,
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};
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static void
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g84_fifo_nonstall_block(struct nvkm_event *event, int type, int index)
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{
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struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event);
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unsigned long flags;
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spin_lock_irqsave(&fifo->lock, flags);
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nvkm_mask(fifo->engine.subdev.device, 0x002140, 0x40000000, 0x00000000);
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spin_unlock_irqrestore(&fifo->lock, flags);
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}
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static void
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g84_fifo_nonstall_allow(struct nvkm_event *event, int type, int index)
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{
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struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event);
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unsigned long flags;
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spin_lock_irqsave(&fifo->lock, flags);
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nvkm_mask(fifo->engine.subdev.device, 0x002140, 0x40000000, 0x40000000);
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spin_unlock_irqrestore(&fifo->lock, flags);
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}
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const struct nvkm_event_func
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g84_fifo_nonstall = {
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.init = g84_fifo_nonstall_allow,
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.fini = g84_fifo_nonstall_block,
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};
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static int
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g84_fifo_runl_ctor(struct nvkm_fifo *fifo)
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{
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struct nvkm_runl *runl;
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runl = nvkm_runl_new(fifo, 0, 0, 0);
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if (IS_ERR(runl))
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return PTR_ERR(runl);
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nvkm_runl_add(runl, 0, fifo->func->engn_sw, NVKM_ENGINE_SW, 0);
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nvkm_runl_add(runl, 0, fifo->func->engn_sw, NVKM_ENGINE_DMAOBJ, 0);
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nvkm_runl_add(runl, 1, fifo->func->engn, NVKM_ENGINE_GR, 0);
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nvkm_runl_add(runl, 2, fifo->func->engn, NVKM_ENGINE_MPEG, 0);
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nvkm_runl_add(runl, 3, fifo->func->engn, NVKM_ENGINE_ME, 0);
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nvkm_runl_add(runl, 4, fifo->func->engn, NVKM_ENGINE_VP, 0);
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nvkm_runl_add(runl, 5, fifo->func->engn, NVKM_ENGINE_CIPHER, 0);
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nvkm_runl_add(runl, 6, fifo->func->engn, NVKM_ENGINE_BSP, 0);
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return 0;
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}
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static const struct nvkm_fifo_func
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g84_fifo = {
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.chid_nr = nv50_fifo_chid_nr,
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.chid_ctor = nv50_fifo_chid_ctor,
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.runl_ctor = g84_fifo_runl_ctor,
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.init = nv50_fifo_init,
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.intr = nv04_fifo_intr,
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.pause = nv04_fifo_pause,
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.start = nv04_fifo_start,
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.nonstall = &g84_fifo_nonstall,
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.runl = &nv50_runl,
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.engn = &g84_engn,
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.engn_sw = &nv50_engn_sw,
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.cgrp = {{ }, &nv04_cgrp },
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.chan = {{ 0, 0, G82_CHANNEL_GPFIFO }, &g84_chan },
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};
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int
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g84_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_fifo **pfifo)
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{
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return nvkm_fifo_new_(&g84_fifo, device, type, inst, pfifo);
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}
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