114 lines
3.5 KiB
C
114 lines
3.5 KiB
C
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "priv.h"
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#include "cgrp.h"
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#include "chan.h"
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#include "runl.h"
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#include <core/gpuobj.h>
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#include <subdev/instmem.h>
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#include "regsnv04.h"
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#include <nvif/class.h>
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static int
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nv10_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv)
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{
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struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc;
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const u32 base = chan->id * 32;
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chan->ramfc_offset = base;
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nvkm_kmap(ramfc);
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nvkm_wo32(ramfc, base + 0x00, offset);
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nvkm_wo32(ramfc, base + 0x04, offset);
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nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4);
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nvkm_wo32(ramfc, base + 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
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NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
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#ifdef __BIG_ENDIAN
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NV_PFIFO_CACHE1_BIG_ENDIAN |
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#endif
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NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
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nvkm_done(ramfc);
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return 0;
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}
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static const struct nvkm_chan_func_ramfc
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nv10_chan_ramfc = {
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.layout = (const struct nvkm_ramfc_layout[]) {
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{ 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
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{ 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
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{ 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
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{ 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
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{ 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
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{ 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE },
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{ 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH },
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{ 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE },
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{ 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 },
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{}
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},
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.write = nv10_chan_ramfc_write,
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.clear = nv04_chan_ramfc_clear,
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.ctxdma = true,
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};
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static const struct nvkm_chan_func
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nv10_chan = {
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.inst = &nv04_chan_inst,
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.userd = &nv04_chan_userd,
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.ramfc = &nv10_chan_ramfc,
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.start = nv04_chan_start,
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.stop = nv04_chan_stop,
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};
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int
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nv10_fifo_chid_nr(struct nvkm_fifo *fifo)
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{
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return 32;
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}
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static const struct nvkm_fifo_func
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nv10_fifo = {
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.chid_nr = nv10_fifo_chid_nr,
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.chid_ctor = nv04_fifo_chid_ctor,
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.runl_ctor = nv04_fifo_runl_ctor,
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.init = nv04_fifo_init,
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.intr = nv04_fifo_intr,
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.pause = nv04_fifo_pause,
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.start = nv04_fifo_start,
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.runl = &nv04_runl,
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.engn = &nv04_engn,
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.engn_sw = &nv04_engn,
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.cgrp = {{ }, &nv04_cgrp },
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.chan = {{ 0, 0, NV10_CHANNEL_DMA }, &nv10_chan },
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};
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int
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nv10_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_fifo **pfifo)
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{
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return nvkm_fifo_new_(&nv10_fifo, device, type, inst, pfifo);
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}
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