319 lines
9.6 KiB
C
319 lines
9.6 KiB
C
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <core/memory.h>
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#include <subdev/acr.h>
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#include <subdev/timer.h>
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#include <nvfw/flcn.h>
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#include <nvfw/sec2.h>
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int
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gp102_sec2_nofw(struct nvkm_sec2 *sec2, int ver,
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const struct nvkm_sec2_fwif *fwif)
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{
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nvkm_warn(&sec2->engine.subdev, "firmware unavailable\n");
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return 0;
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}
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static int
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gp102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nvfw_falcon_msg *hdr)
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{
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struct nv_sec2_acr_bootstrap_falcon_msg *msg =
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container_of(hdr, typeof(*msg), msg.hdr);
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struct nvkm_subdev *subdev = priv;
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const char *name = nvkm_acr_lsf_id(msg->falcon_id);
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if (msg->error_code) {
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nvkm_error(subdev, "ACR_BOOTSTRAP_FALCON failed for "
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"falcon %d [%s]: %08x\n",
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msg->falcon_id, name, msg->error_code);
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return -EINVAL;
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}
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nvkm_debug(subdev, "%s booted\n", name);
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return 0;
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}
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static int
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gp102_sec2_acr_bootstrap_falcon(struct nvkm_falcon *falcon,
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enum nvkm_acr_lsf_id id)
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{
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struct nvkm_sec2 *sec2 = container_of(falcon, typeof(*sec2), falcon);
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struct nv_sec2_acr_bootstrap_falcon_cmd cmd = {
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.cmd.hdr.unit_id = sec2->func->unit_acr,
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.cmd.hdr.size = sizeof(cmd),
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.cmd.cmd_type = NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON,
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.flags = NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES,
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.falcon_id = id,
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};
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return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr,
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gp102_sec2_acr_bootstrap_falcon_callback,
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&sec2->engine.subdev,
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msecs_to_jiffies(1000));
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}
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static void
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gp102_sec2_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
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{
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struct loader_config_v1 hdr;
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nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
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hdr.code_dma_base = hdr.code_dma_base + adjust;
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hdr.data_dma_base = hdr.data_dma_base + adjust;
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hdr.overlay_dma_base = hdr.overlay_dma_base + adjust;
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nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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loader_config_v1_dump(&acr->subdev, &hdr);
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}
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static void
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gp102_sec2_acr_bld_write(struct nvkm_acr *acr, u32 bld,
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struct nvkm_acr_lsfw *lsfw)
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{
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const struct loader_config_v1 hdr = {
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.dma_idx = FALCON_SEC2_DMAIDX_UCODE,
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.code_dma_base = lsfw->offset.img + lsfw->app_start_offset,
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.code_size_total = lsfw->app_size,
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.code_size_to_load = lsfw->app_resident_code_size,
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.code_entry_point = lsfw->app_imem_entry,
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.data_dma_base = lsfw->offset.img + lsfw->app_start_offset +
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lsfw->app_resident_data_offset,
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.data_size = lsfw->app_resident_data_size,
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.overlay_dma_base = lsfw->offset.img + lsfw->app_start_offset,
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.argc = 1,
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.argv = lsfw->falcon->func->emem_addr,
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};
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nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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}
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static const struct nvkm_acr_lsf_func
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gp102_sec2_acr_0 = {
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.bld_size = sizeof(struct loader_config_v1),
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.bld_write = gp102_sec2_acr_bld_write,
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.bld_patch = gp102_sec2_acr_bld_patch,
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.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
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BIT_ULL(NVKM_ACR_LSF_GPCCS) |
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BIT_ULL(NVKM_ACR_LSF_SEC2),
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.bootstrap_falcon = gp102_sec2_acr_bootstrap_falcon,
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};
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int
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gp102_sec2_initmsg(struct nvkm_sec2 *sec2)
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{
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struct nv_sec2_init_msg msg;
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int ret, i;
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ret = nvkm_falcon_msgq_recv_initmsg(sec2->msgq, &msg, sizeof(msg));
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if (ret)
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return ret;
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if (msg.hdr.unit_id != NV_SEC2_UNIT_INIT ||
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msg.msg_type != NV_SEC2_INIT_MSG_INIT)
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(msg.queue_info); i++) {
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if (msg.queue_info[i].id == NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ) {
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nvkm_falcon_msgq_init(sec2->msgq,
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msg.queue_info[i].index,
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msg.queue_info[i].offset,
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msg.queue_info[i].size);
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} else {
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nvkm_falcon_cmdq_init(sec2->cmdq,
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msg.queue_info[i].index,
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msg.queue_info[i].offset,
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msg.queue_info[i].size);
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}
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}
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return 0;
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}
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irqreturn_t
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gp102_sec2_intr(struct nvkm_inth *inth)
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{
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struct nvkm_sec2 *sec2 = container_of(inth, typeof(*sec2), engine.subdev.inth);
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struct nvkm_subdev *subdev = &sec2->engine.subdev;
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struct nvkm_falcon *falcon = &sec2->falcon;
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u32 disp = nvkm_falcon_rd32(falcon, 0x01c);
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u32 intr = nvkm_falcon_rd32(falcon, 0x008) & disp & ~(disp >> 16);
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if (intr & 0x00000040) {
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if (unlikely(atomic_read(&sec2->initmsg) == 0)) {
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int ret = sec2->func->initmsg(sec2);
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if (ret)
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nvkm_error(subdev, "error parsing init message: %d\n", ret);
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atomic_set(&sec2->initmsg, ret ?: 1);
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}
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if (atomic_read(&sec2->initmsg) > 0) {
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if (!nvkm_falcon_msgq_empty(sec2->msgq))
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nvkm_falcon_msgq_recv(sec2->msgq);
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}
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nvkm_falcon_wr32(falcon, 0x004, 0x00000040);
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intr &= ~0x00000040;
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}
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if (intr & 0x00000010) {
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if (atomic_read(&sec2->running)) {
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FLCN_ERR(falcon, "halted");
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gm200_flcn_tracepc(falcon);
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}
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nvkm_falcon_wr32(falcon, 0x004, 0x00000010);
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intr &= ~0x00000010;
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}
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if (intr) {
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nvkm_error(subdev, "unhandled intr %08x\n", intr);
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nvkm_falcon_wr32(falcon, 0x004, intr);
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}
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return IRQ_HANDLED;
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}
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static const struct nvkm_falcon_func
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gp102_sec2_flcn = {
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.disable = gm200_flcn_disable,
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.enable = gm200_flcn_enable,
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.reset_pmc = true,
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.reset_eng = gp102_flcn_reset_eng,
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.reset_wait_mem_scrubbing = gm200_flcn_reset_wait_mem_scrubbing,
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.debug = 0x408,
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.bind_inst = gm200_flcn_bind_inst,
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.bind_stat = gm200_flcn_bind_stat,
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.bind_intr = true,
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.imem_pio = &gm200_flcn_imem_pio,
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.dmem_pio = &gm200_flcn_dmem_pio,
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.emem_addr = 0x01000000,
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.emem_pio = &gp102_flcn_emem_pio,
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.start = nvkm_falcon_v1_start,
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.cmdq = { 0xa00, 0xa04, 8 },
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.msgq = { 0xa30, 0xa34, 8 },
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};
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const struct nvkm_sec2_func
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gp102_sec2 = {
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.flcn = &gp102_sec2_flcn,
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.unit_unload = NV_SEC2_UNIT_UNLOAD,
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.unit_acr = NV_SEC2_UNIT_ACR,
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.intr = gp102_sec2_intr,
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.initmsg = gp102_sec2_initmsg,
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};
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MODULE_FIRMWARE("nvidia/gp102/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/gp102/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/gp102/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/gp104/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/gp104/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/gp104/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/gp106/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/gp106/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/gp106/sec2/sig.bin");
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MODULE_FIRMWARE("nvidia/gp107/sec2/desc.bin");
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MODULE_FIRMWARE("nvidia/gp107/sec2/image.bin");
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MODULE_FIRMWARE("nvidia/gp107/sec2/sig.bin");
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void
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gp102_sec2_acr_bld_patch_1(struct nvkm_acr *acr, u32 bld, s64 adjust)
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{
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struct flcn_bl_dmem_desc_v2 hdr;
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nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
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hdr.code_dma_base = hdr.code_dma_base + adjust;
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hdr.data_dma_base = hdr.data_dma_base + adjust;
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nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr);
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}
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void
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gp102_sec2_acr_bld_write_1(struct nvkm_acr *acr, u32 bld,
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struct nvkm_acr_lsfw *lsfw)
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{
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const struct flcn_bl_dmem_desc_v2 hdr = {
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.ctx_dma = FALCON_SEC2_DMAIDX_UCODE,
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.code_dma_base = lsfw->offset.img + lsfw->app_start_offset,
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.non_sec_code_off = lsfw->app_resident_code_offset,
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.non_sec_code_size = lsfw->app_resident_code_size,
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.code_entry_point = lsfw->app_imem_entry,
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.data_dma_base = lsfw->offset.img + lsfw->app_start_offset +
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lsfw->app_resident_data_offset,
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.data_size = lsfw->app_resident_data_size,
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.argc = 1,
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.argv = lsfw->falcon->func->emem_addr,
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};
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nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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}
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const struct nvkm_acr_lsf_func
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gp102_sec2_acr_1 = {
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.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
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.bld_write = gp102_sec2_acr_bld_write_1,
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.bld_patch = gp102_sec2_acr_bld_patch_1,
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.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
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BIT_ULL(NVKM_ACR_LSF_GPCCS) |
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BIT_ULL(NVKM_ACR_LSF_SEC2),
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.bootstrap_falcon = gp102_sec2_acr_bootstrap_falcon,
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};
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int
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gp102_sec2_load(struct nvkm_sec2 *sec2, int ver,
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const struct nvkm_sec2_fwif *fwif)
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{
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return nvkm_acr_lsfw_load_sig_image_desc_v1(&sec2->engine.subdev,
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&sec2->falcon,
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NVKM_ACR_LSF_SEC2, "sec2/",
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ver, fwif->acr);
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}
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MODULE_FIRMWARE("nvidia/gp102/sec2/desc-1.bin");
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MODULE_FIRMWARE("nvidia/gp102/sec2/image-1.bin");
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MODULE_FIRMWARE("nvidia/gp102/sec2/sig-1.bin");
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MODULE_FIRMWARE("nvidia/gp104/sec2/desc-1.bin");
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MODULE_FIRMWARE("nvidia/gp104/sec2/image-1.bin");
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MODULE_FIRMWARE("nvidia/gp104/sec2/sig-1.bin");
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MODULE_FIRMWARE("nvidia/gp106/sec2/desc-1.bin");
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MODULE_FIRMWARE("nvidia/gp106/sec2/image-1.bin");
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MODULE_FIRMWARE("nvidia/gp106/sec2/sig-1.bin");
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MODULE_FIRMWARE("nvidia/gp107/sec2/desc-1.bin");
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MODULE_FIRMWARE("nvidia/gp107/sec2/image-1.bin");
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MODULE_FIRMWARE("nvidia/gp107/sec2/sig-1.bin");
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static const struct nvkm_sec2_fwif
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gp102_sec2_fwif[] = {
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{ 1, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_1 },
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{ 0, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_0 },
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{ -1, gp102_sec2_nofw, &gp102_sec2 },
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{}
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};
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int
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gp102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_sec2 **psec2)
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{
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return nvkm_sec2_new_(gp102_sec2_fwif, device, type, inst, 0, psec2);
|
||
|
|
}
|