441 lines
12 KiB
C
441 lines
12 KiB
C
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/*
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* Copyright 2005-2006 Erik Waling
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* Copyright 2006 Stephane Marchesin
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* Copyright 2007-2009 Stuart Bennett
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <subdev/bios.h>
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#include <subdev/bios/bit.h>
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#include <subdev/bios/bmp.h>
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#include <subdev/bios/pll.h>
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#include <subdev/vga.h>
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struct pll_mapping {
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u8 type;
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u32 reg;
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};
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static struct pll_mapping
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nv04_pll_mapping[] = {
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{ PLL_CORE , 0x680500 },
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{ PLL_MEMORY, 0x680504 },
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{ PLL_VPLL0 , 0x680508 },
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{ PLL_VPLL1 , 0x680520 },
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{}
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};
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static struct pll_mapping
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nv40_pll_mapping[] = {
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{ PLL_CORE , 0x004000 },
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{ PLL_MEMORY, 0x004020 },
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{ PLL_VPLL0 , 0x680508 },
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{ PLL_VPLL1 , 0x680520 },
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{}
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};
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static struct pll_mapping
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nv50_pll_mapping[] = {
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{ PLL_CORE , 0x004028 },
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{ PLL_SHADER, 0x004020 },
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{ PLL_UNK03 , 0x004000 },
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{ PLL_MEMORY, 0x004008 },
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{ PLL_UNK40 , 0x00e810 },
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{ PLL_UNK41 , 0x00e818 },
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{ PLL_UNK42 , 0x00e824 },
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{ PLL_VPLL0 , 0x614100 },
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{ PLL_VPLL1 , 0x614900 },
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{}
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};
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static struct pll_mapping
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g84_pll_mapping[] = {
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{ PLL_CORE , 0x004028 },
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{ PLL_SHADER, 0x004020 },
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{ PLL_MEMORY, 0x004008 },
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{ PLL_VDEC , 0x004030 },
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{ PLL_UNK41 , 0x00e818 },
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{ PLL_VPLL0 , 0x614100 },
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{ PLL_VPLL1 , 0x614900 },
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{}
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};
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static u32
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pll_limits_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
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{
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struct bit_entry bit_C;
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u32 data = 0x0000;
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if (!bit_entry(bios, 'C', &bit_C)) {
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if (bit_C.version == 1 && bit_C.length >= 10)
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data = nvbios_rd16(bios, bit_C.offset + 8);
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if (bit_C.version == 2 && bit_C.length >= 4)
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data = nvbios_rd32(bios, bit_C.offset + 0);
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if (data) {
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*ver = nvbios_rd08(bios, data + 0);
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*hdr = nvbios_rd08(bios, data + 1);
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*len = nvbios_rd08(bios, data + 2);
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*cnt = nvbios_rd08(bios, data + 3);
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return data;
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}
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}
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if (bmp_version(bios) >= 0x0524) {
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data = nvbios_rd16(bios, bios->bmp_offset + 142);
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if (data) {
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*ver = nvbios_rd08(bios, data + 0);
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*hdr = 1;
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*cnt = 1;
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*len = 0x18;
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return data;
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}
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}
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*ver = 0x00;
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return data;
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}
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static struct pll_mapping *
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pll_map(struct nvkm_bios *bios)
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{
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struct nvkm_device *device = bios->subdev.device;
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switch (device->card_type) {
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case NV_04:
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case NV_10:
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case NV_11:
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case NV_20:
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case NV_30:
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return nv04_pll_mapping;
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case NV_40:
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return nv40_pll_mapping;
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case NV_50:
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if (device->chipset == 0x50)
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return nv50_pll_mapping;
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else
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if (device->chipset < 0xa3 ||
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device->chipset == 0xaa ||
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device->chipset == 0xac)
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return g84_pll_mapping;
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fallthrough;
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default:
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return NULL;
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}
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}
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static u32
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pll_map_reg(struct nvkm_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len)
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{
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struct pll_mapping *map;
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u8 hdr, cnt;
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u32 data;
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data = pll_limits_table(bios, ver, &hdr, &cnt, len);
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if (data && *ver >= 0x30) {
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data += hdr;
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while (cnt--) {
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if (nvbios_rd32(bios, data + 3) == reg) {
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*type = nvbios_rd08(bios, data + 0);
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return data;
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}
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data += *len;
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}
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return 0x0000;
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}
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map = pll_map(bios);
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while (map && map->reg) {
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if (map->reg == reg && *ver >= 0x20) {
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u32 addr = (data += hdr);
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*type = map->type;
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while (cnt--) {
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if (nvbios_rd32(bios, data) == map->reg)
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return data;
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data += *len;
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}
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return addr;
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} else
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if (map->reg == reg) {
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*type = map->type;
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return data + 1;
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}
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map++;
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}
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return 0x0000;
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}
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static u32
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pll_map_type(struct nvkm_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len)
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{
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struct pll_mapping *map;
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u8 hdr, cnt;
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u32 data;
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data = pll_limits_table(bios, ver, &hdr, &cnt, len);
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if (data && *ver >= 0x30) {
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data += hdr;
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while (cnt--) {
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if (nvbios_rd08(bios, data + 0) == type) {
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if (*ver < 0x50)
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*reg = nvbios_rd32(bios, data + 3);
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else
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*reg = 0;
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return data;
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}
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data += *len;
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}
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return 0x0000;
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}
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map = pll_map(bios);
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while (map && map->reg) {
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if (map->type == type && *ver >= 0x20) {
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u32 addr = (data += hdr);
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*reg = map->reg;
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while (cnt--) {
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if (nvbios_rd32(bios, data) == map->reg)
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return data;
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data += *len;
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}
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return addr;
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} else
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if (map->type == type) {
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*reg = map->reg;
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return data + 1;
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}
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map++;
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}
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return 0x0000;
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}
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int
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nvbios_pll_parse(struct nvkm_bios *bios, u32 type, struct nvbios_pll *info)
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{
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struct nvkm_subdev *subdev = &bios->subdev;
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struct nvkm_device *device = subdev->device;
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u8 ver, len;
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u32 reg = type;
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u32 data;
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if (type > PLL_MAX) {
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reg = type;
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data = pll_map_reg(bios, reg, &type, &ver, &len);
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} else {
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data = pll_map_type(bios, type, ®, &ver, &len);
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}
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if (ver && !data)
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return -ENOENT;
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memset(info, 0, sizeof(*info));
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info->type = type;
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info->reg = reg;
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switch (ver) {
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case 0x00:
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break;
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case 0x10:
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case 0x11:
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info->vco1.min_freq = nvbios_rd32(bios, data + 0);
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info->vco1.max_freq = nvbios_rd32(bios, data + 4);
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info->vco2.min_freq = nvbios_rd32(bios, data + 8);
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info->vco2.max_freq = nvbios_rd32(bios, data + 12);
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info->vco1.min_inputfreq = nvbios_rd32(bios, data + 16);
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info->vco2.min_inputfreq = nvbios_rd32(bios, data + 20);
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info->vco1.max_inputfreq = INT_MAX;
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info->vco2.max_inputfreq = INT_MAX;
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info->max_p = 0x7;
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info->max_p_usable = 0x6;
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/* these values taken from nv30/31/36 */
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switch (bios->version.chip) {
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case 0x36:
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info->vco1.min_n = 0x5;
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break;
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default:
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info->vco1.min_n = 0x1;
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break;
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}
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info->vco1.max_n = 0xff;
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info->vco1.min_m = 0x1;
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info->vco1.max_m = 0xd;
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/*
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* On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
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* table version (apart from nv35)), N2 is compared to
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* maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
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* save a comparison
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*/
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info->vco2.min_n = 0x4;
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switch (bios->version.chip) {
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case 0x30:
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case 0x35:
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info->vco2.max_n = 0x1f;
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break;
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default:
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info->vco2.max_n = 0x28;
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break;
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}
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info->vco2.min_m = 0x1;
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info->vco2.max_m = 0x4;
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break;
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case 0x20:
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case 0x21:
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info->vco1.min_freq = nvbios_rd16(bios, data + 4) * 1000;
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info->vco1.max_freq = nvbios_rd16(bios, data + 6) * 1000;
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info->vco2.min_freq = nvbios_rd16(bios, data + 8) * 1000;
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info->vco2.max_freq = nvbios_rd16(bios, data + 10) * 1000;
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info->vco1.min_inputfreq = nvbios_rd16(bios, data + 12) * 1000;
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info->vco2.min_inputfreq = nvbios_rd16(bios, data + 14) * 1000;
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info->vco1.max_inputfreq = nvbios_rd16(bios, data + 16) * 1000;
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info->vco2.max_inputfreq = nvbios_rd16(bios, data + 18) * 1000;
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info->vco1.min_n = nvbios_rd08(bios, data + 20);
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info->vco1.max_n = nvbios_rd08(bios, data + 21);
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info->vco1.min_m = nvbios_rd08(bios, data + 22);
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info->vco1.max_m = nvbios_rd08(bios, data + 23);
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info->vco2.min_n = nvbios_rd08(bios, data + 24);
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info->vco2.max_n = nvbios_rd08(bios, data + 25);
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info->vco2.min_m = nvbios_rd08(bios, data + 26);
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info->vco2.max_m = nvbios_rd08(bios, data + 27);
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info->max_p = nvbios_rd08(bios, data + 29);
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info->max_p_usable = info->max_p;
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if (bios->version.chip < 0x60)
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info->max_p_usable = 0x6;
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info->bias_p = nvbios_rd08(bios, data + 30);
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if (len > 0x22)
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info->refclk = nvbios_rd32(bios, data + 31);
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break;
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case 0x30:
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data = nvbios_rd16(bios, data + 1);
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info->vco1.min_freq = nvbios_rd16(bios, data + 0) * 1000;
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info->vco1.max_freq = nvbios_rd16(bios, data + 2) * 1000;
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info->vco2.min_freq = nvbios_rd16(bios, data + 4) * 1000;
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info->vco2.max_freq = nvbios_rd16(bios, data + 6) * 1000;
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info->vco1.min_inputfreq = nvbios_rd16(bios, data + 8) * 1000;
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info->vco2.min_inputfreq = nvbios_rd16(bios, data + 10) * 1000;
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info->vco1.max_inputfreq = nvbios_rd16(bios, data + 12) * 1000;
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info->vco2.max_inputfreq = nvbios_rd16(bios, data + 14) * 1000;
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info->vco1.min_n = nvbios_rd08(bios, data + 16);
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info->vco1.max_n = nvbios_rd08(bios, data + 17);
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info->vco1.min_m = nvbios_rd08(bios, data + 18);
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info->vco1.max_m = nvbios_rd08(bios, data + 19);
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info->vco2.min_n = nvbios_rd08(bios, data + 20);
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info->vco2.max_n = nvbios_rd08(bios, data + 21);
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info->vco2.min_m = nvbios_rd08(bios, data + 22);
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info->vco2.max_m = nvbios_rd08(bios, data + 23);
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info->max_p_usable = info->max_p = nvbios_rd08(bios, data + 25);
|
||
|
|
info->bias_p = nvbios_rd08(bios, data + 27);
|
||
|
|
info->refclk = nvbios_rd32(bios, data + 28);
|
||
|
|
break;
|
||
|
|
case 0x40:
|
||
|
|
info->refclk = nvbios_rd16(bios, data + 9) * 1000;
|
||
|
|
data = nvbios_rd16(bios, data + 1);
|
||
|
|
|
||
|
|
info->vco1.min_freq = nvbios_rd16(bios, data + 0) * 1000;
|
||
|
|
info->vco1.max_freq = nvbios_rd16(bios, data + 2) * 1000;
|
||
|
|
info->vco1.min_inputfreq = nvbios_rd16(bios, data + 4) * 1000;
|
||
|
|
info->vco1.max_inputfreq = nvbios_rd16(bios, data + 6) * 1000;
|
||
|
|
info->vco1.min_m = nvbios_rd08(bios, data + 8);
|
||
|
|
info->vco1.max_m = nvbios_rd08(bios, data + 9);
|
||
|
|
info->vco1.min_n = nvbios_rd08(bios, data + 10);
|
||
|
|
info->vco1.max_n = nvbios_rd08(bios, data + 11);
|
||
|
|
info->min_p = nvbios_rd08(bios, data + 12);
|
||
|
|
info->max_p = nvbios_rd08(bios, data + 13);
|
||
|
|
break;
|
||
|
|
case 0x50:
|
||
|
|
info->refclk = nvbios_rd16(bios, data + 1) * 1000;
|
||
|
|
/* info->refclk_alt = nvbios_rd16(bios, data + 3) * 1000; */
|
||
|
|
info->vco1.min_freq = nvbios_rd16(bios, data + 5) * 1000;
|
||
|
|
info->vco1.max_freq = nvbios_rd16(bios, data + 7) * 1000;
|
||
|
|
info->vco1.min_inputfreq = nvbios_rd16(bios, data + 9) * 1000;
|
||
|
|
info->vco1.max_inputfreq = nvbios_rd16(bios, data + 11) * 1000;
|
||
|
|
info->vco1.min_m = nvbios_rd08(bios, data + 13);
|
||
|
|
info->vco1.max_m = nvbios_rd08(bios, data + 14);
|
||
|
|
info->vco1.min_n = nvbios_rd08(bios, data + 15);
|
||
|
|
info->vco1.max_n = nvbios_rd08(bios, data + 16);
|
||
|
|
info->min_p = nvbios_rd08(bios, data + 17);
|
||
|
|
info->max_p = nvbios_rd08(bios, data + 18);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
nvkm_error(subdev, "unknown pll limits version 0x%02x\n", ver);
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!info->refclk) {
|
||
|
|
info->refclk = device->crystal;
|
||
|
|
if (bios->version.chip == 0x51) {
|
||
|
|
u32 sel_clk = nvkm_rd32(device, 0x680524);
|
||
|
|
if ((info->reg == 0x680508 && sel_clk & 0x20) ||
|
||
|
|
(info->reg == 0x680520 && sel_clk & 0x80)) {
|
||
|
|
if (nvkm_rdvgac(device, 0, 0x27) < 0xa3)
|
||
|
|
info->refclk = 200000;
|
||
|
|
else
|
||
|
|
info->refclk = 25000;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* By now any valid limit table ought to have set a max frequency for
|
||
|
|
* vco1, so if it's zero it's either a pre limit table bios, or one
|
||
|
|
* with an empty limit table (seen on nv18)
|
||
|
|
*/
|
||
|
|
if (!info->vco1.max_freq) {
|
||
|
|
info->vco1.max_freq = nvbios_rd32(bios, bios->bmp_offset + 67);
|
||
|
|
info->vco1.min_freq = nvbios_rd32(bios, bios->bmp_offset + 71);
|
||
|
|
if (bmp_version(bios) < 0x0506) {
|
||
|
|
info->vco1.max_freq = 256000;
|
||
|
|
info->vco1.min_freq = 128000;
|
||
|
|
}
|
||
|
|
|
||
|
|
info->vco1.min_inputfreq = 0;
|
||
|
|
info->vco1.max_inputfreq = INT_MAX;
|
||
|
|
info->vco1.min_n = 0x1;
|
||
|
|
info->vco1.max_n = 0xff;
|
||
|
|
info->vco1.min_m = 0x1;
|
||
|
|
|
||
|
|
if (device->crystal == 13500) {
|
||
|
|
/* nv05 does this, nv11 doesn't, nv10 unknown */
|
||
|
|
if (bios->version.chip < 0x11)
|
||
|
|
info->vco1.min_m = 0x7;
|
||
|
|
info->vco1.max_m = 0xd;
|
||
|
|
} else {
|
||
|
|
if (bios->version.chip < 0x11)
|
||
|
|
info->vco1.min_m = 0x8;
|
||
|
|
info->vco1.max_m = 0xe;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (bios->version.chip < 0x17 ||
|
||
|
|
bios->version.chip == 0x1a ||
|
||
|
|
bios->version.chip == 0x20)
|
||
|
|
info->max_p = 4;
|
||
|
|
else
|
||
|
|
info->max_p = 5;
|
||
|
|
info->max_p_usable = info->max_p;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|