259 lines
9.9 KiB
C
259 lines
9.9 KiB
C
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/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <subdev/bios.h>
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#include <subdev/bios/bit.h>
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#include <subdev/bios/rammap.h>
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u32
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nvbios_rammapTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr,
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u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
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{
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struct bit_entry bit_P;
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u32 rammap = 0x0000;
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if (!bit_entry(bios, 'P', &bit_P)) {
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if (bit_P.version == 2)
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rammap = nvbios_rd32(bios, bit_P.offset + 4);
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if (rammap) {
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*ver = nvbios_rd08(bios, rammap + 0);
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switch (*ver) {
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case 0x10:
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case 0x11:
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*hdr = nvbios_rd08(bios, rammap + 1);
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*cnt = nvbios_rd08(bios, rammap + 5);
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*len = nvbios_rd08(bios, rammap + 2);
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*snr = nvbios_rd08(bios, rammap + 4);
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*ssz = nvbios_rd08(bios, rammap + 3);
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return rammap;
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default:
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break;
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}
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}
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}
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return 0x0000;
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}
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u32
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nvbios_rammapEe(struct nvkm_bios *bios, int idx,
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u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
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{
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u8 snr, ssz;
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u32 rammap = nvbios_rammapTe(bios, ver, hdr, cnt, len, &snr, &ssz);
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if (rammap && idx < *cnt) {
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rammap = rammap + *hdr + (idx * (*len + (snr * ssz)));
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*hdr = *len;
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*cnt = snr;
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*len = ssz;
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return rammap;
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}
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return 0x0000;
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}
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/* Pretend a performance mode is also a rammap entry, helps coalesce entries
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* later on */
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u32
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nvbios_rammapEp_from_perf(struct nvkm_bios *bios, u32 data, u8 size,
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struct nvbios_ramcfg *p)
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{
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memset(p, 0x00, sizeof(*p));
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p->rammap_00_16_20 = (nvbios_rd08(bios, data + 0x16) & 0x20) >> 5;
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p->rammap_00_16_40 = (nvbios_rd08(bios, data + 0x16) & 0x40) >> 6;
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p->rammap_00_17_02 = (nvbios_rd08(bios, data + 0x17) & 0x02) >> 1;
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return data;
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}
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u32
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nvbios_rammapEp(struct nvkm_bios *bios, int idx,
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u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p)
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{
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u32 data = nvbios_rammapEe(bios, idx, ver, hdr, cnt, len), temp;
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memset(p, 0x00, sizeof(*p));
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p->rammap_ver = *ver;
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p->rammap_hdr = *hdr;
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switch (!!data * *ver) {
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case 0x10:
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p->rammap_min = nvbios_rd16(bios, data + 0x00);
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p->rammap_max = nvbios_rd16(bios, data + 0x02);
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p->rammap_10_04_02 = (nvbios_rd08(bios, data + 0x04) & 0x02) >> 1;
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p->rammap_10_04_08 = (nvbios_rd08(bios, data + 0x04) & 0x08) >> 3;
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break;
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case 0x11:
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p->rammap_min = nvbios_rd16(bios, data + 0x00);
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p->rammap_max = nvbios_rd16(bios, data + 0x02);
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p->rammap_11_08_01 = (nvbios_rd08(bios, data + 0x08) & 0x01) >> 0;
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p->rammap_11_08_0c = (nvbios_rd08(bios, data + 0x08) & 0x0c) >> 2;
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p->rammap_11_08_10 = (nvbios_rd08(bios, data + 0x08) & 0x10) >> 4;
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temp = nvbios_rd32(bios, data + 0x09);
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p->rammap_11_09_01ff = (temp & 0x000001ff) >> 0;
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p->rammap_11_0a_03fe = (temp & 0x0003fe00) >> 9;
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p->rammap_11_0a_0400 = (temp & 0x00040000) >> 18;
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p->rammap_11_0a_0800 = (temp & 0x00080000) >> 19;
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p->rammap_11_0b_01f0 = (temp & 0x01f00000) >> 20;
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p->rammap_11_0b_0200 = (temp & 0x02000000) >> 25;
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p->rammap_11_0b_0400 = (temp & 0x04000000) >> 26;
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p->rammap_11_0b_0800 = (temp & 0x08000000) >> 27;
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p->rammap_11_0d = nvbios_rd08(bios, data + 0x0d);
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p->rammap_11_0e = nvbios_rd08(bios, data + 0x0e);
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p->rammap_11_0f = nvbios_rd08(bios, data + 0x0f);
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p->rammap_11_11_0c = (nvbios_rd08(bios, data + 0x11) & 0x0c) >> 2;
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break;
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default:
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data = 0;
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break;
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}
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return data;
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}
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u32
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nvbios_rammapEm(struct nvkm_bios *bios, u16 mhz,
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u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *info)
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{
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int idx = 0;
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u32 data;
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while ((data = nvbios_rammapEp(bios, idx++, ver, hdr, cnt, len, info))) {
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if (mhz >= info->rammap_min && mhz <= info->rammap_max)
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break;
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}
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return data;
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}
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u32
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nvbios_rammapSe(struct nvkm_bios *bios, u32 data,
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u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, u8 *ver, u8 *hdr)
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{
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if (idx < ecnt) {
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data = data + ehdr + (idx * elen);
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*ver = ever;
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*hdr = elen;
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return data;
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}
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return 0;
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}
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u32
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nvbios_rammapSp_from_perf(struct nvkm_bios *bios, u32 data, u8 size, int idx,
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struct nvbios_ramcfg *p)
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{
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data += (idx * size);
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if (size < 11)
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return 0x00000000;
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p->ramcfg_ver = 0;
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p->ramcfg_timing = nvbios_rd08(bios, data + 0x01);
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p->ramcfg_00_03_01 = (nvbios_rd08(bios, data + 0x03) & 0x01) >> 0;
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p->ramcfg_00_03_02 = (nvbios_rd08(bios, data + 0x03) & 0x02) >> 1;
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p->ramcfg_DLLoff = (nvbios_rd08(bios, data + 0x03) & 0x04) >> 2;
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p->ramcfg_00_03_08 = (nvbios_rd08(bios, data + 0x03) & 0x08) >> 3;
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p->ramcfg_RON = (nvbios_rd08(bios, data + 0x03) & 0x10) >> 3;
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p->ramcfg_FBVDDQ = (nvbios_rd08(bios, data + 0x03) & 0x80) >> 7;
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p->ramcfg_00_04_02 = (nvbios_rd08(bios, data + 0x04) & 0x02) >> 1;
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p->ramcfg_00_04_04 = (nvbios_rd08(bios, data + 0x04) & 0x04) >> 2;
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p->ramcfg_00_04_20 = (nvbios_rd08(bios, data + 0x04) & 0x20) >> 5;
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p->ramcfg_00_05 = (nvbios_rd08(bios, data + 0x05) & 0xff) >> 0;
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p->ramcfg_00_06 = (nvbios_rd08(bios, data + 0x06) & 0xff) >> 0;
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p->ramcfg_00_07 = (nvbios_rd08(bios, data + 0x07) & 0xff) >> 0;
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p->ramcfg_00_08 = (nvbios_rd08(bios, data + 0x08) & 0xff) >> 0;
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p->ramcfg_00_09 = (nvbios_rd08(bios, data + 0x09) & 0xff) >> 0;
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p->ramcfg_00_0a_0f = (nvbios_rd08(bios, data + 0x0a) & 0x0f) >> 0;
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p->ramcfg_00_0a_f0 = (nvbios_rd08(bios, data + 0x0a) & 0xf0) >> 4;
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return data;
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}
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u32
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nvbios_rammapSp(struct nvkm_bios *bios, u32 data,
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u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx,
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u8 *ver, u8 *hdr, struct nvbios_ramcfg *p)
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{
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data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr);
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p->ramcfg_ver = *ver;
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p->ramcfg_hdr = *hdr;
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switch (!!data * *ver) {
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case 0x10:
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p->ramcfg_timing = nvbios_rd08(bios, data + 0x01);
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p->ramcfg_10_02_01 = (nvbios_rd08(bios, data + 0x02) & 0x01) >> 0;
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p->ramcfg_10_02_02 = (nvbios_rd08(bios, data + 0x02) & 0x02) >> 1;
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p->ramcfg_10_02_04 = (nvbios_rd08(bios, data + 0x02) & 0x04) >> 2;
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p->ramcfg_10_02_08 = (nvbios_rd08(bios, data + 0x02) & 0x08) >> 3;
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p->ramcfg_10_02_10 = (nvbios_rd08(bios, data + 0x02) & 0x10) >> 4;
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p->ramcfg_10_02_20 = (nvbios_rd08(bios, data + 0x02) & 0x20) >> 5;
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p->ramcfg_DLLoff = (nvbios_rd08(bios, data + 0x02) & 0x40) >> 6;
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p->ramcfg_10_03_0f = (nvbios_rd08(bios, data + 0x03) & 0x0f) >> 0;
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p->ramcfg_10_04_01 = (nvbios_rd08(bios, data + 0x04) & 0x01) >> 0;
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p->ramcfg_FBVDDQ = (nvbios_rd08(bios, data + 0x04) & 0x08) >> 3;
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p->ramcfg_10_05 = (nvbios_rd08(bios, data + 0x05) & 0xff) >> 0;
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p->ramcfg_10_06 = (nvbios_rd08(bios, data + 0x06) & 0xff) >> 0;
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p->ramcfg_10_07 = (nvbios_rd08(bios, data + 0x07) & 0xff) >> 0;
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p->ramcfg_10_08 = (nvbios_rd08(bios, data + 0x08) & 0xff) >> 0;
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p->ramcfg_10_09_0f = (nvbios_rd08(bios, data + 0x09) & 0x0f) >> 0;
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p->ramcfg_10_09_f0 = (nvbios_rd08(bios, data + 0x09) & 0xf0) >> 4;
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break;
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case 0x11:
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p->ramcfg_timing = nvbios_rd08(bios, data + 0x00);
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p->ramcfg_11_01_01 = (nvbios_rd08(bios, data + 0x01) & 0x01) >> 0;
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p->ramcfg_11_01_02 = (nvbios_rd08(bios, data + 0x01) & 0x02) >> 1;
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p->ramcfg_11_01_04 = (nvbios_rd08(bios, data + 0x01) & 0x04) >> 2;
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p->ramcfg_11_01_08 = (nvbios_rd08(bios, data + 0x01) & 0x08) >> 3;
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p->ramcfg_11_01_10 = (nvbios_rd08(bios, data + 0x01) & 0x10) >> 4;
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p->ramcfg_DLLoff = (nvbios_rd08(bios, data + 0x01) & 0x20) >> 5;
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p->ramcfg_11_01_40 = (nvbios_rd08(bios, data + 0x01) & 0x40) >> 6;
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p->ramcfg_11_01_80 = (nvbios_rd08(bios, data + 0x01) & 0x80) >> 7;
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p->ramcfg_11_02_03 = (nvbios_rd08(bios, data + 0x02) & 0x03) >> 0;
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p->ramcfg_11_02_04 = (nvbios_rd08(bios, data + 0x02) & 0x04) >> 2;
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p->ramcfg_11_02_08 = (nvbios_rd08(bios, data + 0x02) & 0x08) >> 3;
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p->ramcfg_11_02_10 = (nvbios_rd08(bios, data + 0x02) & 0x10) >> 4;
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p->ramcfg_11_02_40 = (nvbios_rd08(bios, data + 0x02) & 0x40) >> 6;
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p->ramcfg_11_02_80 = (nvbios_rd08(bios, data + 0x02) & 0x80) >> 7;
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p->ramcfg_11_03_0f = (nvbios_rd08(bios, data + 0x03) & 0x0f) >> 0;
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p->ramcfg_11_03_30 = (nvbios_rd08(bios, data + 0x03) & 0x30) >> 4;
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p->ramcfg_11_03_c0 = (nvbios_rd08(bios, data + 0x03) & 0xc0) >> 6;
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p->ramcfg_11_03_f0 = (nvbios_rd08(bios, data + 0x03) & 0xf0) >> 4;
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p->ramcfg_11_04 = (nvbios_rd08(bios, data + 0x04) & 0xff) >> 0;
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p->ramcfg_11_06 = (nvbios_rd08(bios, data + 0x06) & 0xff) >> 0;
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p->ramcfg_11_07_02 = (nvbios_rd08(bios, data + 0x07) & 0x02) >> 1;
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p->ramcfg_11_07_04 = (nvbios_rd08(bios, data + 0x07) & 0x04) >> 2;
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p->ramcfg_11_07_08 = (nvbios_rd08(bios, data + 0x07) & 0x08) >> 3;
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p->ramcfg_11_07_10 = (nvbios_rd08(bios, data + 0x07) & 0x10) >> 4;
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p->ramcfg_11_07_40 = (nvbios_rd08(bios, data + 0x07) & 0x40) >> 6;
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p->ramcfg_11_07_80 = (nvbios_rd08(bios, data + 0x07) & 0x80) >> 7;
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p->ramcfg_11_08_01 = (nvbios_rd08(bios, data + 0x08) & 0x01) >> 0;
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p->ramcfg_11_08_02 = (nvbios_rd08(bios, data + 0x08) & 0x02) >> 1;
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p->ramcfg_11_08_04 = (nvbios_rd08(bios, data + 0x08) & 0x04) >> 2;
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p->ramcfg_11_08_08 = (nvbios_rd08(bios, data + 0x08) & 0x08) >> 3;
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p->ramcfg_11_08_10 = (nvbios_rd08(bios, data + 0x08) & 0x10) >> 4;
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p->ramcfg_11_08_20 = (nvbios_rd08(bios, data + 0x08) & 0x20) >> 5;
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p->ramcfg_11_09 = (nvbios_rd08(bios, data + 0x09) & 0xff) >> 0;
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break;
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default:
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data = 0;
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break;
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}
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return data;
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}
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