372 lines
10 KiB
C
372 lines
10 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
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/*
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* Copyright(c) 2015, 2016 Intel Corporation.
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*/
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#ifndef __PLATFORM_H
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#define __PLATFORM_H
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#define METADATA_TABLE_FIELD_START_SHIFT 0
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#define METADATA_TABLE_FIELD_START_LEN_BITS 15
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#define METADATA_TABLE_FIELD_LEN_SHIFT 16
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#define METADATA_TABLE_FIELD_LEN_LEN_BITS 16
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/* Header structure */
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#define PLATFORM_CONFIG_HEADER_RECORD_IDX_SHIFT 0
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#define PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS 6
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#define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT 16
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#define PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS 12
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#define PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT 28
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#define PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS 4
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enum platform_config_table_type_encoding {
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PLATFORM_CONFIG_TABLE_RESERVED,
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PLATFORM_CONFIG_SYSTEM_TABLE,
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PLATFORM_CONFIG_PORT_TABLE,
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PLATFORM_CONFIG_RX_PRESET_TABLE,
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PLATFORM_CONFIG_TX_PRESET_TABLE,
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PLATFORM_CONFIG_QSFP_ATTEN_TABLE,
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PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE,
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PLATFORM_CONFIG_TABLE_MAX
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};
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enum platform_config_system_table_fields {
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SYSTEM_TABLE_RESERVED,
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SYSTEM_TABLE_NODE_STRING,
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SYSTEM_TABLE_SYSTEM_IMAGE_GUID,
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SYSTEM_TABLE_NODE_GUID,
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SYSTEM_TABLE_REVISION,
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SYSTEM_TABLE_VENDOR_OUI,
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SYSTEM_TABLE_META_VERSION,
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SYSTEM_TABLE_DEVICE_ID,
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SYSTEM_TABLE_PARTITION_ENFORCEMENT_CAP,
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SYSTEM_TABLE_QSFP_POWER_CLASS_MAX,
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SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_12G,
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SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G,
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SYSTEM_TABLE_VARIABLE_TABLE_ENTRIES_PER_PORT,
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SYSTEM_TABLE_MAX
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};
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enum platform_config_port_table_fields {
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PORT_TABLE_RESERVED,
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PORT_TABLE_PORT_TYPE,
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PORT_TABLE_LOCAL_ATTEN_12G,
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PORT_TABLE_LOCAL_ATTEN_25G,
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PORT_TABLE_LINK_SPEED_SUPPORTED,
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PORT_TABLE_LINK_WIDTH_SUPPORTED,
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PORT_TABLE_AUTO_LANE_SHEDDING_ENABLED,
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PORT_TABLE_EXTERNAL_LOOPBACK_ALLOWED,
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PORT_TABLE_VL_CAP,
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PORT_TABLE_MTU_CAP,
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PORT_TABLE_TX_LANE_ENABLE_MASK,
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PORT_TABLE_LOCAL_MAX_TIMEOUT,
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PORT_TABLE_REMOTE_ATTEN_12G,
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PORT_TABLE_REMOTE_ATTEN_25G,
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PORT_TABLE_TX_PRESET_IDX_ACTIVE_NO_EQ,
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PORT_TABLE_TX_PRESET_IDX_ACTIVE_EQ,
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PORT_TABLE_RX_PRESET_IDX,
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PORT_TABLE_CABLE_REACH_CLASS,
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PORT_TABLE_MAX
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};
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enum platform_config_rx_preset_table_fields {
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RX_PRESET_TABLE_RESERVED,
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RX_PRESET_TABLE_QSFP_RX_CDR_APPLY,
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RX_PRESET_TABLE_QSFP_RX_EMP_APPLY,
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RX_PRESET_TABLE_QSFP_RX_AMP_APPLY,
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RX_PRESET_TABLE_QSFP_RX_CDR,
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RX_PRESET_TABLE_QSFP_RX_EMP,
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RX_PRESET_TABLE_QSFP_RX_AMP,
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RX_PRESET_TABLE_MAX
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};
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enum platform_config_tx_preset_table_fields {
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TX_PRESET_TABLE_RESERVED,
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TX_PRESET_TABLE_PRECUR,
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TX_PRESET_TABLE_ATTN,
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TX_PRESET_TABLE_POSTCUR,
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TX_PRESET_TABLE_QSFP_TX_CDR_APPLY,
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TX_PRESET_TABLE_QSFP_TX_EQ_APPLY,
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TX_PRESET_TABLE_QSFP_TX_CDR,
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TX_PRESET_TABLE_QSFP_TX_EQ,
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TX_PRESET_TABLE_MAX
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};
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enum platform_config_qsfp_attn_table_fields {
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QSFP_ATTEN_TABLE_RESERVED,
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QSFP_ATTEN_TABLE_TX_PRESET_IDX,
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QSFP_ATTEN_TABLE_RX_PRESET_IDX,
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QSFP_ATTEN_TABLE_MAX
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};
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enum platform_config_variable_settings_table_fields {
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VARIABLE_SETTINGS_TABLE_RESERVED,
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VARIABLE_SETTINGS_TABLE_TX_PRESET_IDX,
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VARIABLE_SETTINGS_TABLE_RX_PRESET_IDX,
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VARIABLE_SETTINGS_TABLE_MAX
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};
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struct platform_config {
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size_t size;
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const u8 *data;
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};
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struct platform_config_data {
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u32 *table;
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u32 *table_metadata;
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u32 num_table;
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};
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/*
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* This struct acts as a quick reference into the platform_data binary image
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* and is populated by parse_platform_config(...) depending on the specific
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* META_VERSION
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*/
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struct platform_config_cache {
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u8 cache_valid;
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struct platform_config_data config_tables[PLATFORM_CONFIG_TABLE_MAX];
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};
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/* This section defines default values and encodings for the
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* fields defined for each table above
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*/
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/*
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* =====================================================
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* System table encodings
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* =====================================================
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*/
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#define PLATFORM_CONFIG_MAGIC_NUM 0x3d4f5041
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#define PLATFORM_CONFIG_MAGIC_NUMBER_LEN 4
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/*
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* These power classes are the same as defined in SFF 8636 spec rev 2.4
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* describing byte 129 in table 6-16, except enumerated in a different order
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*/
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enum platform_config_qsfp_power_class_encoding {
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QSFP_POWER_CLASS_1 = 1,
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QSFP_POWER_CLASS_2,
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QSFP_POWER_CLASS_3,
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QSFP_POWER_CLASS_4,
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QSFP_POWER_CLASS_5,
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QSFP_POWER_CLASS_6,
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QSFP_POWER_CLASS_7
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};
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/*
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* ====================================================
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* Port table encodings
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* ====================================================
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*/
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enum platform_config_port_type_encoding {
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PORT_TYPE_UNKNOWN,
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PORT_TYPE_DISCONNECTED,
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PORT_TYPE_FIXED,
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PORT_TYPE_VARIABLE,
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PORT_TYPE_QSFP,
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PORT_TYPE_MAX
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};
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enum platform_config_link_speed_supported_encoding {
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LINK_SPEED_SUPP_12G = 1,
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LINK_SPEED_SUPP_25G,
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LINK_SPEED_SUPP_12G_25G,
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LINK_SPEED_SUPP_MAX
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};
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/*
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* This is a subset (not strict) of the link downgrades
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* supported. The link downgrades supported are expected
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* to be supplied to the driver by another entity such as
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* the fabric manager
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*/
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enum platform_config_link_width_supported_encoding {
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LINK_WIDTH_SUPP_1X = 1,
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LINK_WIDTH_SUPP_2X,
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LINK_WIDTH_SUPP_2X_1X,
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LINK_WIDTH_SUPP_3X,
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LINK_WIDTH_SUPP_3X_1X,
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LINK_WIDTH_SUPP_3X_2X,
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LINK_WIDTH_SUPP_3X_2X_1X,
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LINK_WIDTH_SUPP_4X,
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LINK_WIDTH_SUPP_4X_1X,
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LINK_WIDTH_SUPP_4X_2X,
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LINK_WIDTH_SUPP_4X_2X_1X,
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LINK_WIDTH_SUPP_4X_3X,
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LINK_WIDTH_SUPP_4X_3X_1X,
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LINK_WIDTH_SUPP_4X_3X_2X,
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LINK_WIDTH_SUPP_4X_3X_2X_1X,
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LINK_WIDTH_SUPP_MAX
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};
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enum platform_config_virtual_lane_capability_encoding {
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VL_CAP_VL0 = 1,
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VL_CAP_VL0_1,
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VL_CAP_VL0_2,
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VL_CAP_VL0_3,
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VL_CAP_VL0_4,
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VL_CAP_VL0_5,
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VL_CAP_VL0_6,
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VL_CAP_VL0_7,
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VL_CAP_VL0_8,
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VL_CAP_VL0_9,
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VL_CAP_VL0_10,
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VL_CAP_VL0_11,
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VL_CAP_VL0_12,
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VL_CAP_VL0_13,
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VL_CAP_VL0_14,
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VL_CAP_MAX
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};
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/* Max MTU */
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enum platform_config_mtu_capability_encoding {
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MTU_CAP_256 = 1,
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MTU_CAP_512 = 2,
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MTU_CAP_1024 = 3,
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MTU_CAP_2048 = 4,
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MTU_CAP_4096 = 5,
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MTU_CAP_8192 = 6,
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MTU_CAP_10240 = 7
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};
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enum platform_config_local_max_timeout_encoding {
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LOCAL_MAX_TIMEOUT_10_MS = 1,
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LOCAL_MAX_TIMEOUT_100_MS,
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LOCAL_MAX_TIMEOUT_1_S,
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LOCAL_MAX_TIMEOUT_10_S,
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LOCAL_MAX_TIMEOUT_100_S,
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LOCAL_MAX_TIMEOUT_1000_S
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};
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enum link_tuning_encoding {
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OPA_PASSIVE_TUNING,
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OPA_ACTIVE_TUNING,
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OPA_UNKNOWN_TUNING
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};
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/*
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* Shifts and masks for the link SI tuning values stuffed into the ASIC scratch
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* registers for integrated platforms
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*/
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#define PORT0_PORT_TYPE_SHIFT 0
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#define PORT0_LOCAL_ATTEN_SHIFT 4
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#define PORT0_REMOTE_ATTEN_SHIFT 10
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#define PORT0_DEFAULT_ATTEN_SHIFT 32
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#define PORT1_PORT_TYPE_SHIFT 16
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#define PORT1_LOCAL_ATTEN_SHIFT 20
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#define PORT1_REMOTE_ATTEN_SHIFT 26
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#define PORT1_DEFAULT_ATTEN_SHIFT 40
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#define PORT0_PORT_TYPE_MASK 0xFUL
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#define PORT0_LOCAL_ATTEN_MASK 0x3FUL
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#define PORT0_REMOTE_ATTEN_MASK 0x3FUL
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#define PORT0_DEFAULT_ATTEN_MASK 0xFFUL
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#define PORT1_PORT_TYPE_MASK 0xFUL
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#define PORT1_LOCAL_ATTEN_MASK 0x3FUL
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#define PORT1_REMOTE_ATTEN_MASK 0x3FUL
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#define PORT1_DEFAULT_ATTEN_MASK 0xFFUL
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#define PORT0_PORT_TYPE_SMASK (PORT0_PORT_TYPE_MASK << \
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PORT0_PORT_TYPE_SHIFT)
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#define PORT0_LOCAL_ATTEN_SMASK (PORT0_LOCAL_ATTEN_MASK << \
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PORT0_LOCAL_ATTEN_SHIFT)
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#define PORT0_REMOTE_ATTEN_SMASK (PORT0_REMOTE_ATTEN_MASK << \
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PORT0_REMOTE_ATTEN_SHIFT)
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#define PORT0_DEFAULT_ATTEN_SMASK (PORT0_DEFAULT_ATTEN_MASK << \
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PORT0_DEFAULT_ATTEN_SHIFT)
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#define PORT1_PORT_TYPE_SMASK (PORT1_PORT_TYPE_MASK << \
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PORT1_PORT_TYPE_SHIFT)
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#define PORT1_LOCAL_ATTEN_SMASK (PORT1_LOCAL_ATTEN_MASK << \
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PORT1_LOCAL_ATTEN_SHIFT)
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#define PORT1_REMOTE_ATTEN_SMASK (PORT1_REMOTE_ATTEN_MASK << \
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PORT1_REMOTE_ATTEN_SHIFT)
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#define PORT1_DEFAULT_ATTEN_SMASK (PORT1_DEFAULT_ATTEN_MASK << \
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PORT1_DEFAULT_ATTEN_SHIFT)
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#define QSFP_MAX_POWER_SHIFT 0
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#define TX_NO_EQ_SHIFT 4
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#define TX_EQ_SHIFT 25
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#define RX_SHIFT 46
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#define QSFP_MAX_POWER_MASK 0xFUL
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#define TX_NO_EQ_MASK 0x1FFFFFUL
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#define TX_EQ_MASK 0x1FFFFFUL
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#define RX_MASK 0xFFFFUL
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#define QSFP_MAX_POWER_SMASK (QSFP_MAX_POWER_MASK << \
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QSFP_MAX_POWER_SHIFT)
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#define TX_NO_EQ_SMASK (TX_NO_EQ_MASK << TX_NO_EQ_SHIFT)
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#define TX_EQ_SMASK (TX_EQ_MASK << TX_EQ_SHIFT)
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#define RX_SMASK (RX_MASK << RX_SHIFT)
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#define TX_PRECUR_SHIFT 0
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#define TX_ATTN_SHIFT 4
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#define QSFP_TX_CDR_APPLY_SHIFT 9
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#define QSFP_TX_EQ_APPLY_SHIFT 10
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#define QSFP_TX_CDR_SHIFT 11
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#define QSFP_TX_EQ_SHIFT 12
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#define TX_POSTCUR_SHIFT 16
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#define TX_PRECUR_MASK 0xFUL
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#define TX_ATTN_MASK 0x1FUL
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#define QSFP_TX_CDR_APPLY_MASK 0x1UL
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#define QSFP_TX_EQ_APPLY_MASK 0x1UL
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#define QSFP_TX_CDR_MASK 0x1UL
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#define QSFP_TX_EQ_MASK 0xFUL
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#define TX_POSTCUR_MASK 0x1FUL
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#define TX_PRECUR_SMASK (TX_PRECUR_MASK << TX_PRECUR_SHIFT)
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#define TX_ATTN_SMASK (TX_ATTN_MASK << TX_ATTN_SHIFT)
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#define QSFP_TX_CDR_APPLY_SMASK (QSFP_TX_CDR_APPLY_MASK << \
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QSFP_TX_CDR_APPLY_SHIFT)
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#define QSFP_TX_EQ_APPLY_SMASK (QSFP_TX_EQ_APPLY_MASK << \
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QSFP_TX_EQ_APPLY_SHIFT)
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#define QSFP_TX_CDR_SMASK (QSFP_TX_CDR_MASK << QSFP_TX_CDR_SHIFT)
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#define QSFP_TX_EQ_SMASK (QSFP_TX_EQ_MASK << QSFP_TX_EQ_SHIFT)
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#define TX_POSTCUR_SMASK (TX_POSTCUR_MASK << TX_POSTCUR_SHIFT)
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#define QSFP_RX_CDR_APPLY_SHIFT 0
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#define QSFP_RX_EMP_APPLY_SHIFT 1
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#define QSFP_RX_AMP_APPLY_SHIFT 2
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#define QSFP_RX_CDR_SHIFT 3
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#define QSFP_RX_EMP_SHIFT 4
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#define QSFP_RX_AMP_SHIFT 8
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#define QSFP_RX_CDR_APPLY_MASK 0x1UL
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#define QSFP_RX_EMP_APPLY_MASK 0x1UL
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#define QSFP_RX_AMP_APPLY_MASK 0x1UL
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#define QSFP_RX_CDR_MASK 0x1UL
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#define QSFP_RX_EMP_MASK 0xFUL
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#define QSFP_RX_AMP_MASK 0x3UL
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#define QSFP_RX_CDR_APPLY_SMASK (QSFP_RX_CDR_APPLY_MASK << \
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QSFP_RX_CDR_APPLY_SHIFT)
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#define QSFP_RX_EMP_APPLY_SMASK (QSFP_RX_EMP_APPLY_MASK << \
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QSFP_RX_EMP_APPLY_SHIFT)
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#define QSFP_RX_AMP_APPLY_SMASK (QSFP_RX_AMP_APPLY_MASK << \
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QSFP_RX_AMP_APPLY_SHIFT)
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#define QSFP_RX_CDR_SMASK (QSFP_RX_CDR_MASK << QSFP_RX_CDR_SHIFT)
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#define QSFP_RX_EMP_SMASK (QSFP_RX_EMP_MASK << QSFP_RX_EMP_SHIFT)
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#define QSFP_RX_AMP_SMASK (QSFP_RX_AMP_MASK << QSFP_RX_AMP_SHIFT)
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#define BITMAP_VERSION 1
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#define BITMAP_VERSION_SHIFT 44
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#define BITMAP_VERSION_MASK 0xFUL
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#define BITMAP_VERSION_SMASK (BITMAP_VERSION_MASK << \
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BITMAP_VERSION_SHIFT)
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#define CHECKSUM_SHIFT 48
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#define CHECKSUM_MASK 0xFFFFUL
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#define CHECKSUM_SMASK (CHECKSUM_MASK << CHECKSUM_SHIFT)
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/* platform.c */
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void get_platform_config(struct hfi1_devdata *dd);
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void free_platform_config(struct hfi1_devdata *dd);
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void get_port_type(struct hfi1_pportdata *ppd);
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int set_qsfp_tx(struct hfi1_pportdata *ppd, int on);
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void tune_serdes(struct hfi1_pportdata *ppd);
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#endif /*__PLATFORM_H*/
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