346 lines
9.6 KiB
C
346 lines
9.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (C) 2019-2020 NVIDIA CORPORATION. All rights reserved.
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <soc/tegra/mc.h>
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#include "arm-smmu.h"
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/*
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* Tegra194 has three ARM MMU-500 Instances.
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* Two of them are used together and must be programmed identically for
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* interleaved IOVA accesses across them and translates accesses from
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* non-isochronous HW devices.
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* Third one is used for translating accesses from isochronous HW devices.
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*
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* In addition, the SMMU driver needs to coordinate with the memory controller
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* driver to ensure that the right SID override is programmed for any given
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* memory client. This is necessary to allow for use-case such as seamlessly
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* handing over the display controller configuration from the firmware to the
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* kernel.
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*
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* This implementation supports programming of the two instances that must
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* be programmed identically and takes care of invoking the memory controller
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* driver for SID override programming after devices have been attached to an
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* SMMU instance.
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*/
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#define MAX_SMMU_INSTANCES 2
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struct nvidia_smmu {
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struct arm_smmu_device smmu;
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void __iomem *bases[MAX_SMMU_INSTANCES];
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unsigned int num_instances;
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struct tegra_mc *mc;
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};
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static inline struct nvidia_smmu *to_nvidia_smmu(struct arm_smmu_device *smmu)
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{
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return container_of(smmu, struct nvidia_smmu, smmu);
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}
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static inline void __iomem *nvidia_smmu_page(struct arm_smmu_device *smmu,
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unsigned int inst, int page)
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{
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struct nvidia_smmu *nvidia_smmu;
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nvidia_smmu = container_of(smmu, struct nvidia_smmu, smmu);
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return nvidia_smmu->bases[inst] + (page << smmu->pgshift);
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}
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static u32 nvidia_smmu_read_reg(struct arm_smmu_device *smmu,
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int page, int offset)
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{
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void __iomem *reg = nvidia_smmu_page(smmu, 0, page) + offset;
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return readl_relaxed(reg);
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}
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static void nvidia_smmu_write_reg(struct arm_smmu_device *smmu,
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int page, int offset, u32 val)
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{
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struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
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unsigned int i;
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for (i = 0; i < nvidia->num_instances; i++) {
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void __iomem *reg = nvidia_smmu_page(smmu, i, page) + offset;
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writel_relaxed(val, reg);
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}
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}
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static u64 nvidia_smmu_read_reg64(struct arm_smmu_device *smmu,
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int page, int offset)
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{
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void __iomem *reg = nvidia_smmu_page(smmu, 0, page) + offset;
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return readq_relaxed(reg);
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}
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static void nvidia_smmu_write_reg64(struct arm_smmu_device *smmu,
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int page, int offset, u64 val)
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{
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struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
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unsigned int i;
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for (i = 0; i < nvidia->num_instances; i++) {
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void __iomem *reg = nvidia_smmu_page(smmu, i, page) + offset;
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writeq_relaxed(val, reg);
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}
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}
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static void nvidia_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,
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int sync, int status)
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{
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struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
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unsigned int delay;
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arm_smmu_writel(smmu, page, sync, 0);
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for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) {
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unsigned int spin_cnt;
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for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) {
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u32 val = 0;
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unsigned int i;
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for (i = 0; i < nvidia->num_instances; i++) {
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void __iomem *reg;
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reg = nvidia_smmu_page(smmu, i, page) + status;
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val |= readl_relaxed(reg);
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}
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if (!(val & ARM_SMMU_sTLBGSTATUS_GSACTIVE))
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return;
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cpu_relax();
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}
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udelay(delay);
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}
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dev_err_ratelimited(smmu->dev,
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"TLB sync timed out -- SMMU may be deadlocked\n");
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}
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static int nvidia_smmu_reset(struct arm_smmu_device *smmu)
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{
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struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
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unsigned int i;
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for (i = 0; i < nvidia->num_instances; i++) {
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u32 val;
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void __iomem *reg = nvidia_smmu_page(smmu, i, ARM_SMMU_GR0) +
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ARM_SMMU_GR0_sGFSR;
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/* clear global FSR */
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val = readl_relaxed(reg);
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writel_relaxed(val, reg);
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}
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return 0;
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}
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static irqreturn_t nvidia_smmu_global_fault_inst(int irq,
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struct arm_smmu_device *smmu,
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int inst)
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{
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u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
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void __iomem *gr0_base = nvidia_smmu_page(smmu, inst, 0);
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gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
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if (!gfsr)
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return IRQ_NONE;
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gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
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gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
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gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
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dev_err_ratelimited(smmu->dev,
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"Unexpected global fault, this could be serious\n");
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dev_err_ratelimited(smmu->dev,
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"\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
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gfsr, gfsynr0, gfsynr1, gfsynr2);
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writel_relaxed(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
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return IRQ_HANDLED;
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}
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static irqreturn_t nvidia_smmu_global_fault(int irq, void *dev)
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{
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unsigned int inst;
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irqreturn_t ret = IRQ_NONE;
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struct arm_smmu_device *smmu = dev;
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struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
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for (inst = 0; inst < nvidia->num_instances; inst++) {
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irqreturn_t irq_ret;
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irq_ret = nvidia_smmu_global_fault_inst(irq, smmu, inst);
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if (irq_ret == IRQ_HANDLED)
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
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struct arm_smmu_device *smmu,
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int idx, int inst)
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{
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u32 fsr, fsynr, cbfrsynra;
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unsigned long iova;
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void __iomem *gr1_base = nvidia_smmu_page(smmu, inst, 1);
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void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage + idx);
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fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
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if (!(fsr & ARM_SMMU_FSR_FAULT))
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return IRQ_NONE;
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fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
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iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
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cbfrsynra = readl_relaxed(gr1_base + ARM_SMMU_GR1_CBFRSYNRA(idx));
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dev_err_ratelimited(smmu->dev,
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"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
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fsr, iova, fsynr, cbfrsynra, idx);
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writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);
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return IRQ_HANDLED;
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}
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static irqreturn_t nvidia_smmu_context_fault(int irq, void *dev)
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{
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int idx;
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unsigned int inst;
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irqreturn_t ret = IRQ_NONE;
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struct arm_smmu_device *smmu;
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struct iommu_domain *domain = dev;
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struct arm_smmu_domain *smmu_domain;
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struct nvidia_smmu *nvidia;
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smmu_domain = container_of(domain, struct arm_smmu_domain, domain);
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smmu = smmu_domain->smmu;
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nvidia = to_nvidia_smmu(smmu);
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for (inst = 0; inst < nvidia->num_instances; inst++) {
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irqreturn_t irq_ret;
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/*
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* Interrupt line is shared between all contexts.
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* Check for faults across all contexts.
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*/
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for (idx = 0; idx < smmu->num_context_banks; idx++) {
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irq_ret = nvidia_smmu_context_fault_bank(irq, smmu,
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idx, inst);
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if (irq_ret == IRQ_HANDLED)
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ret = IRQ_HANDLED;
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}
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}
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return ret;
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}
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static void nvidia_smmu_probe_finalize(struct arm_smmu_device *smmu, struct device *dev)
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{
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struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
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int err;
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err = tegra_mc_probe_device(nvidia->mc, dev);
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if (err < 0)
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dev_err(smmu->dev, "memory controller probe failed for %s: %d\n",
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dev_name(dev), err);
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}
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static int nvidia_smmu_init_context(struct arm_smmu_domain *smmu_domain,
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struct io_pgtable_cfg *pgtbl_cfg,
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struct device *dev)
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{
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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const struct device_node *np = smmu->dev->of_node;
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/*
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* Tegra194 and Tegra234 SoCs have the erratum that causes walk cache
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* entries to not be invalidated correctly. The problem is that the walk
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* cache index generated for IOVA is not same across translation and
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* invalidation requests. This is leading to page faults when PMD entry
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* is released during unmap and populated with new PTE table during
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* subsequent map request. Disabling large page mappings avoids the
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* release of PMD entry and avoid translations seeing stale PMD entry in
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* walk cache.
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* Fix this by limiting the page mappings to PAGE_SIZE on Tegra194 and
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* Tegra234.
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*/
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if (of_device_is_compatible(np, "nvidia,tegra234-smmu") ||
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of_device_is_compatible(np, "nvidia,tegra194-smmu")) {
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smmu->pgsize_bitmap = PAGE_SIZE;
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pgtbl_cfg->pgsize_bitmap = smmu->pgsize_bitmap;
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}
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return 0;
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}
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static const struct arm_smmu_impl nvidia_smmu_impl = {
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.read_reg = nvidia_smmu_read_reg,
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.write_reg = nvidia_smmu_write_reg,
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.read_reg64 = nvidia_smmu_read_reg64,
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.write_reg64 = nvidia_smmu_write_reg64,
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.reset = nvidia_smmu_reset,
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.tlb_sync = nvidia_smmu_tlb_sync,
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.global_fault = nvidia_smmu_global_fault,
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.context_fault = nvidia_smmu_context_fault,
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.probe_finalize = nvidia_smmu_probe_finalize,
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.init_context = nvidia_smmu_init_context,
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};
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static const struct arm_smmu_impl nvidia_smmu_single_impl = {
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.probe_finalize = nvidia_smmu_probe_finalize,
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.init_context = nvidia_smmu_init_context,
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};
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struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu)
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{
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struct resource *res;
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struct device *dev = smmu->dev;
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struct nvidia_smmu *nvidia_smmu;
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struct platform_device *pdev = to_platform_device(dev);
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unsigned int i;
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nvidia_smmu = devm_krealloc(dev, smmu, sizeof(*nvidia_smmu), GFP_KERNEL);
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if (!nvidia_smmu)
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return ERR_PTR(-ENOMEM);
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nvidia_smmu->mc = devm_tegra_memory_controller_get(dev);
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if (IS_ERR(nvidia_smmu->mc))
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return ERR_CAST(nvidia_smmu->mc);
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/* Instance 0 is ioremapped by arm-smmu.c. */
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nvidia_smmu->bases[0] = smmu->base;
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nvidia_smmu->num_instances++;
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for (i = 1; i < MAX_SMMU_INSTANCES; i++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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if (!res)
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break;
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nvidia_smmu->bases[i] = devm_ioremap_resource(dev, res);
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if (IS_ERR(nvidia_smmu->bases[i]))
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return ERR_CAST(nvidia_smmu->bases[i]);
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nvidia_smmu->num_instances++;
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}
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if (nvidia_smmu->num_instances == 1)
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nvidia_smmu->smmu.impl = &nvidia_smmu_single_impl;
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else
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nvidia_smmu->smmu.impl = &nvidia_smmu_impl;
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return &nvidia_smmu->smmu;
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}
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