40 lines
885 B
C
40 lines
885 B
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _ARM_SMMU_QCOM_H
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#define _ARM_SMMU_QCOM_H
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struct qcom_smmu {
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struct arm_smmu_device smmu;
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const struct qcom_smmu_config *cfg;
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bool bypass_quirk;
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u8 bypass_cbndx;
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u32 stall_enabled;
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};
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enum qcom_smmu_impl_reg_offset {
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QCOM_SMMU_TBU_PWR_STATUS,
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QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,
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QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
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};
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struct qcom_smmu_config {
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const u32 *reg_offset;
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};
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struct qcom_smmu_match_data {
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const struct qcom_smmu_config *cfg;
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const struct arm_smmu_impl *impl;
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const struct arm_smmu_impl *adreno_impl;
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};
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#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
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void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu);
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#else
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static inline void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu) { }
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#endif
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#endif /* _ARM_SMMU_QCOM_H */
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