470 lines
12 KiB
C
470 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#include <linux/mailbox_controller.h>
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#include <linux/platform_device.h>
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#include "mtk-mdp3-cmdq.h"
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#include "mtk-mdp3-comp.h"
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#include "mtk-mdp3-core.h"
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#include "mtk-mdp3-m2m.h"
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#define MDP_PATH_MAX_COMPS IMG_MAX_COMPONENTS
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struct mdp_path {
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struct mdp_dev *mdp_dev;
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struct mdp_comp_ctx comps[MDP_PATH_MAX_COMPS];
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u32 num_comps;
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const struct img_config *config;
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const struct img_ipi_frameparam *param;
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const struct v4l2_rect *composes[IMG_MAX_HW_OUTPUTS];
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struct v4l2_rect bounds[IMG_MAX_HW_OUTPUTS];
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};
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#define has_op(ctx, op) \
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((ctx)->comp->ops && (ctx)->comp->ops->op)
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#define call_op(ctx, op, ...) \
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(has_op(ctx, op) ? (ctx)->comp->ops->op(ctx, ##__VA_ARGS__) : 0)
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static bool is_output_disabled(const struct img_compparam *param, u32 count)
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{
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return (count < param->num_subfrms) ?
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(param->frame.output_disable ||
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param->subfrms[count].tile_disable) :
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true;
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}
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static int mdp_path_subfrm_require(const struct mdp_path *path,
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struct mdp_cmdq_cmd *cmd,
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s32 *mutex_id, u32 count)
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{
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const struct img_config *config = path->config;
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const struct mdp_comp_ctx *ctx;
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const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data;
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struct device *dev = &path->mdp_dev->pdev->dev;
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struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex;
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int id, index;
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/* Decide which mutex to use based on the current pipeline */
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switch (path->comps[0].comp->id) {
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case MDP_COMP_RDMA0:
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*mutex_id = MDP_PIPE_RDMA0;
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break;
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case MDP_COMP_ISP_IMGI:
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*mutex_id = MDP_PIPE_IMGI;
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break;
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case MDP_COMP_WPEI:
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*mutex_id = MDP_PIPE_WPEI;
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break;
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case MDP_COMP_WPEI2:
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*mutex_id = MDP_PIPE_WPEI2;
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break;
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default:
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dev_err(dev, "Unknown pipeline and no mutex is assigned");
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return -EINVAL;
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}
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/* Set mutex mod */
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for (index = 0; index < config->num_components; index++) {
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ctx = &path->comps[index];
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if (is_output_disabled(ctx->param, count))
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continue;
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id = ctx->comp->id;
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mtk_mutex_write_mod(mutex[*mutex_id],
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data->mdp_mutex_table_idx[id], false);
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}
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mtk_mutex_write_sof(mutex[*mutex_id],
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MUTEX_SOF_IDX_SINGLE_MODE);
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return 0;
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}
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static int mdp_path_subfrm_run(const struct mdp_path *path,
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struct mdp_cmdq_cmd *cmd,
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s32 *mutex_id, u32 count)
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{
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const struct img_config *config = path->config;
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const struct mdp_comp_ctx *ctx;
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struct device *dev = &path->mdp_dev->pdev->dev;
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struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex;
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int index;
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s32 event;
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if (-1 == *mutex_id) {
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dev_err(dev, "Incorrect mutex id");
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return -EINVAL;
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}
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/* Wait WROT SRAM shared to DISP RDMA */
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/* Clear SOF event for each engine */
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for (index = 0; index < config->num_components; index++) {
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ctx = &path->comps[index];
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if (is_output_disabled(ctx->param, count))
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continue;
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event = ctx->comp->gce_event[MDP_GCE_EVENT_SOF];
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if (event != MDP_GCE_NO_EVENT)
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MM_REG_CLEAR(cmd, event);
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}
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/* Enable the mutex */
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mtk_mutex_enable_by_cmdq(mutex[*mutex_id], (void *)&cmd->pkt);
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/* Wait SOF events and clear mutex modules (optional) */
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for (index = 0; index < config->num_components; index++) {
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ctx = &path->comps[index];
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if (is_output_disabled(ctx->param, count))
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continue;
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event = ctx->comp->gce_event[MDP_GCE_EVENT_SOF];
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if (event != MDP_GCE_NO_EVENT)
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MM_REG_WAIT(cmd, event);
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}
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return 0;
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}
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static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path)
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{
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const struct img_config *config = path->config;
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int index, ret;
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if (config->num_components < 1)
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return -EINVAL;
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for (index = 0; index < config->num_components; index++) {
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ret = mdp_comp_ctx_config(mdp, &path->comps[index],
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&config->components[index],
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path->param);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd,
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struct mdp_path *path, u32 count)
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{
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const struct img_config *config = path->config;
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const struct img_mmsys_ctrl *ctrl = &config->ctrls[count];
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const struct img_mux *set;
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struct mdp_comp_ctx *ctx;
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s32 mutex_id;
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int index, ret;
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/* Acquire components */
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ret = mdp_path_subfrm_require(path, cmd, &mutex_id, count);
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if (ret)
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return ret;
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/* Enable mux settings */
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for (index = 0; index < ctrl->num_sets; index++) {
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set = &ctrl->sets[index];
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cmdq_pkt_write_mask(&cmd->pkt, set->subsys_id, set->reg,
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set->value, 0xFFFFFFFF);
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}
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/* Config sub-frame information */
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for (index = (config->num_components - 1); index >= 0; index--) {
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ctx = &path->comps[index];
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if (is_output_disabled(ctx->param, count))
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continue;
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ret = call_op(ctx, config_subfrm, cmd, count);
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if (ret)
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return ret;
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}
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/* Run components */
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ret = mdp_path_subfrm_run(path, cmd, &mutex_id, count);
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if (ret)
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return ret;
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/* Wait components done */
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for (index = 0; index < config->num_components; index++) {
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ctx = &path->comps[index];
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if (is_output_disabled(ctx->param, count))
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continue;
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ret = call_op(ctx, wait_comp_event, cmd);
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if (ret)
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return ret;
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}
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/* Advance to the next sub-frame */
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for (index = 0; index < config->num_components; index++) {
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ctx = &path->comps[index];
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ret = call_op(ctx, advance_subfrm, cmd, count);
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if (ret)
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return ret;
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}
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/* Disable mux settings */
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for (index = 0; index < ctrl->num_sets; index++) {
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set = &ctrl->sets[index];
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cmdq_pkt_write_mask(&cmd->pkt, set->subsys_id, set->reg,
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0, 0xFFFFFFFF);
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}
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return 0;
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}
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static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd,
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struct mdp_path *path)
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{
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const struct img_config *config = path->config;
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struct mdp_comp_ctx *ctx;
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int index, count, ret;
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/* Config path frame */
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/* Reset components */
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for (index = 0; index < config->num_components; index++) {
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ctx = &path->comps[index];
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ret = call_op(ctx, init_comp, cmd);
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if (ret)
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return ret;
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}
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/* Config frame mode */
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for (index = 0; index < config->num_components; index++) {
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const struct v4l2_rect *compose =
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path->composes[ctx->param->outputs[0]];
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ctx = &path->comps[index];
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ret = call_op(ctx, config_frame, cmd, compose);
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if (ret)
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return ret;
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}
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/* Config path sub-frames */
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for (count = 0; count < config->num_subfrms; count++) {
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ret = mdp_path_config_subfrm(cmd, path, count);
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if (ret)
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return ret;
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}
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/* Post processing information */
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for (index = 0; index < config->num_components; index++) {
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ctx = &path->comps[index];
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ret = call_op(ctx, post_process, cmd);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int mdp_cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt,
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size_t size)
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{
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struct device *dev;
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dma_addr_t dma_addr;
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pkt->va_base = kzalloc(size, GFP_KERNEL);
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if (!pkt->va_base)
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return -ENOMEM;
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pkt->buf_size = size;
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pkt->cl = (void *)client;
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dev = client->chan->mbox->dev;
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dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dev, dma_addr)) {
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dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size);
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kfree(pkt->va_base);
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return -ENOMEM;
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}
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pkt->pa_base = dma_addr;
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return 0;
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}
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static void mdp_cmdq_pkt_destroy(struct cmdq_pkt *pkt)
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{
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struct cmdq_client *client = (struct cmdq_client *)pkt->cl;
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dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size,
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DMA_TO_DEVICE);
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kfree(pkt->va_base);
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pkt->va_base = NULL;
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}
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static void mdp_auto_release_work(struct work_struct *work)
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{
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struct mdp_cmdq_cmd *cmd;
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struct mdp_dev *mdp;
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cmd = container_of(work, struct mdp_cmdq_cmd, auto_release_work);
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mdp = cmd->mdp;
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mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
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mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps,
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cmd->num_comps);
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atomic_dec(&mdp->job_count);
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wake_up(&mdp->callback_wq);
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mdp_cmdq_pkt_destroy(&cmd->pkt);
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kfree(cmd->comps);
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cmd->comps = NULL;
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kfree(cmd);
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cmd = NULL;
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}
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static void mdp_handle_cmdq_callback(struct mbox_client *cl, void *mssg)
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{
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struct mdp_cmdq_cmd *cmd;
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struct cmdq_cb_data *data;
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struct mdp_dev *mdp;
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struct device *dev;
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if (!mssg) {
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pr_info("%s:no callback data\n", __func__);
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return;
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}
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data = (struct cmdq_cb_data *)mssg;
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cmd = container_of(data->pkt, struct mdp_cmdq_cmd, pkt);
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mdp = cmd->mdp;
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dev = &mdp->pdev->dev;
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if (cmd->mdp_ctx)
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mdp_m2m_job_finish(cmd->mdp_ctx);
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if (cmd->user_cmdq_cb) {
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struct cmdq_cb_data user_cb_data;
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user_cb_data.sta = data->sta;
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user_cb_data.pkt = data->pkt;
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cmd->user_cmdq_cb(user_cb_data);
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}
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INIT_WORK(&cmd->auto_release_work, mdp_auto_release_work);
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if (!queue_work(mdp->clock_wq, &cmd->auto_release_work)) {
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dev_err(dev, "%s:queue_work fail!\n", __func__);
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mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
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mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps,
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cmd->num_comps);
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atomic_dec(&mdp->job_count);
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wake_up(&mdp->callback_wq);
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mdp_cmdq_pkt_destroy(&cmd->pkt);
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kfree(cmd->comps);
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cmd->comps = NULL;
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kfree(cmd);
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cmd = NULL;
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}
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}
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int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
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{
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struct mdp_path *path = NULL;
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struct mdp_cmdq_cmd *cmd = NULL;
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struct mdp_comp *comps = NULL;
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struct device *dev = &mdp->pdev->dev;
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int i, ret;
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atomic_inc(&mdp->job_count);
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if (atomic_read(&mdp->suspended)) {
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||
|
|
atomic_dec(&mdp->job_count);
|
||
|
|
return -ECANCELED;
|
||
|
|
}
|
||
|
|
|
||
|
|
cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
|
||
|
|
if (!cmd) {
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto err_cancel_job;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = mdp_cmdq_pkt_create(mdp->cmdq_clt, &cmd->pkt, SZ_16K);
|
||
|
|
if (ret)
|
||
|
|
goto err_free_cmd;
|
||
|
|
|
||
|
|
comps = kcalloc(param->config->num_components, sizeof(*comps),
|
||
|
|
GFP_KERNEL);
|
||
|
|
if (!comps) {
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto err_destroy_pkt;
|
||
|
|
}
|
||
|
|
|
||
|
|
path = kzalloc(sizeof(*path), GFP_KERNEL);
|
||
|
|
if (!path) {
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto err_free_comps;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = mtk_mutex_prepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(dev, "Fail to enable mutex clk\n");
|
||
|
|
goto err_free_path;
|
||
|
|
}
|
||
|
|
|
||
|
|
path->mdp_dev = mdp;
|
||
|
|
path->config = param->config;
|
||
|
|
path->param = param->param;
|
||
|
|
for (i = 0; i < param->param->num_outputs; i++) {
|
||
|
|
path->bounds[i].left = 0;
|
||
|
|
path->bounds[i].top = 0;
|
||
|
|
path->bounds[i].width =
|
||
|
|
param->param->outputs[i].buffer.format.width;
|
||
|
|
path->bounds[i].height =
|
||
|
|
param->param->outputs[i].buffer.format.height;
|
||
|
|
path->composes[i] = param->composes[i] ?
|
||
|
|
param->composes[i] : &path->bounds[i];
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = mdp_path_ctx_init(mdp, path);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(dev, "mdp_path_ctx_init error\n");
|
||
|
|
goto err_free_path;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = mdp_path_config(mdp, cmd, path);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(dev, "mdp_path_config error\n");
|
||
|
|
goto err_free_path;
|
||
|
|
}
|
||
|
|
cmdq_pkt_finalize(&cmd->pkt);
|
||
|
|
|
||
|
|
for (i = 0; i < param->config->num_components; i++)
|
||
|
|
memcpy(&comps[i], path->comps[i].comp,
|
||
|
|
sizeof(struct mdp_comp));
|
||
|
|
|
||
|
|
mdp->cmdq_clt->client.rx_callback = mdp_handle_cmdq_callback;
|
||
|
|
cmd->mdp = mdp;
|
||
|
|
cmd->user_cmdq_cb = param->cmdq_cb;
|
||
|
|
cmd->user_cb_data = param->cb_data;
|
||
|
|
cmd->comps = comps;
|
||
|
|
cmd->num_comps = param->config->num_components;
|
||
|
|
cmd->mdp_ctx = param->mdp_ctx;
|
||
|
|
|
||
|
|
ret = mdp_comp_clocks_on(&mdp->pdev->dev, cmd->comps, cmd->num_comps);
|
||
|
|
if (ret)
|
||
|
|
goto err_free_path;
|
||
|
|
|
||
|
|
dma_sync_single_for_device(mdp->cmdq_clt->chan->mbox->dev,
|
||
|
|
cmd->pkt.pa_base, cmd->pkt.cmd_buf_size,
|
||
|
|
DMA_TO_DEVICE);
|
||
|
|
ret = mbox_send_message(mdp->cmdq_clt->chan, &cmd->pkt);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(dev, "mbox send message fail %d!\n", ret);
|
||
|
|
goto err_clock_off;
|
||
|
|
}
|
||
|
|
mbox_client_txdone(mdp->cmdq_clt->chan, 0);
|
||
|
|
|
||
|
|
kfree(path);
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err_clock_off:
|
||
|
|
mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps,
|
||
|
|
cmd->num_comps);
|
||
|
|
err_free_path:
|
||
|
|
mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
|
||
|
|
kfree(path);
|
||
|
|
err_free_comps:
|
||
|
|
kfree(comps);
|
||
|
|
err_destroy_pkt:
|
||
|
|
mdp_cmdq_pkt_destroy(&cmd->pkt);
|
||
|
|
err_free_cmd:
|
||
|
|
kfree(cmd);
|
||
|
|
err_cancel_job:
|
||
|
|
atomic_dec(&mdp->job_count);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(mdp_cmdq_send);
|