285 lines
7.6 KiB
C
285 lines
7.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Hantro VPU HEVC codec driver
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*
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* Copyright (C) 2020 Safran Passenger Innovations LLC
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*/
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#include <linux/types.h>
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#include <media/v4l2-mem2mem.h>
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#include "hantro.h"
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#include "hantro_hw.h"
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#define VERT_FILTER_RAM_SIZE 8 /* bytes per pixel row */
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/*
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* BSD control data of current picture at tile border
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* 128 bits per 4x4 tile = 128/(8*4) bytes per row
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*/
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#define BSD_CTRL_RAM_SIZE 4 /* bytes per pixel row */
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/* tile border coefficients of filter */
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#define VERT_SAO_RAM_SIZE 48 /* bytes per pixel */
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#define SCALING_LIST_SIZE (16 * 64)
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#define MAX_TILE_COLS 20
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#define MAX_TILE_ROWS 22
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void hantro_hevc_ref_init(struct hantro_ctx *ctx)
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{
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struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
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hevc_dec->ref_bufs_used = 0;
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}
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dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx,
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s32 poc)
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{
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struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
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int i;
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/* Find the reference buffer in already known ones */
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for (i = 0; i < NUM_REF_PICTURES; i++) {
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if (hevc_dec->ref_bufs_poc[i] == poc) {
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hevc_dec->ref_bufs_used |= 1 << i;
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return hevc_dec->ref_bufs[i].dma;
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}
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}
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return 0;
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}
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int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr)
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{
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struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
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int i;
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/* Add a new reference buffer */
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for (i = 0; i < NUM_REF_PICTURES; i++) {
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if (!(hevc_dec->ref_bufs_used & 1 << i)) {
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hevc_dec->ref_bufs_used |= 1 << i;
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hevc_dec->ref_bufs_poc[i] = poc;
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hevc_dec->ref_bufs[i].dma = addr;
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return 0;
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}
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}
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return -EINVAL;
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}
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static int tile_buffer_reallocate(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
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const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
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const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
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const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
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unsigned int num_tile_cols = pps->num_tile_columns_minus1 + 1;
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unsigned int height64 = (sps->pic_height_in_luma_samples + 63) & ~63;
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unsigned int size;
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if (num_tile_cols <= 1 ||
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num_tile_cols <= hevc_dec->num_tile_cols_allocated)
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return 0;
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/* Need to reallocate due to tiles passed via PPS */
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if (hevc_dec->tile_filter.cpu) {
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dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size,
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hevc_dec->tile_filter.cpu,
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hevc_dec->tile_filter.dma);
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hevc_dec->tile_filter.cpu = NULL;
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}
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if (hevc_dec->tile_sao.cpu) {
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dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size,
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hevc_dec->tile_sao.cpu,
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hevc_dec->tile_sao.dma);
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hevc_dec->tile_sao.cpu = NULL;
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}
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if (hevc_dec->tile_bsd.cpu) {
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dma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size,
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hevc_dec->tile_bsd.cpu,
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hevc_dec->tile_bsd.dma);
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hevc_dec->tile_bsd.cpu = NULL;
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}
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size = (VERT_FILTER_RAM_SIZE * height64 * (num_tile_cols - 1) * ctx->bit_depth) / 8;
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hevc_dec->tile_filter.cpu = dma_alloc_coherent(vpu->dev, size,
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&hevc_dec->tile_filter.dma,
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GFP_KERNEL);
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if (!hevc_dec->tile_filter.cpu)
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goto err_free_tile_buffers;
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hevc_dec->tile_filter.size = size;
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size = (VERT_SAO_RAM_SIZE * height64 * (num_tile_cols - 1) * ctx->bit_depth) / 8;
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hevc_dec->tile_sao.cpu = dma_alloc_coherent(vpu->dev, size,
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&hevc_dec->tile_sao.dma,
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GFP_KERNEL);
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if (!hevc_dec->tile_sao.cpu)
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goto err_free_tile_buffers;
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hevc_dec->tile_sao.size = size;
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size = BSD_CTRL_RAM_SIZE * height64 * (num_tile_cols - 1);
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hevc_dec->tile_bsd.cpu = dma_alloc_coherent(vpu->dev, size,
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&hevc_dec->tile_bsd.dma,
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GFP_KERNEL);
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if (!hevc_dec->tile_bsd.cpu)
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goto err_free_tile_buffers;
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hevc_dec->tile_bsd.size = size;
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hevc_dec->num_tile_cols_allocated = num_tile_cols;
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return 0;
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err_free_tile_buffers:
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if (hevc_dec->tile_filter.cpu)
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dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size,
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hevc_dec->tile_filter.cpu,
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hevc_dec->tile_filter.dma);
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hevc_dec->tile_filter.cpu = NULL;
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if (hevc_dec->tile_sao.cpu)
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dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size,
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hevc_dec->tile_sao.cpu,
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hevc_dec->tile_sao.dma);
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hevc_dec->tile_sao.cpu = NULL;
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if (hevc_dec->tile_bsd.cpu)
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dma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size,
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hevc_dec->tile_bsd.cpu,
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hevc_dec->tile_bsd.dma);
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hevc_dec->tile_bsd.cpu = NULL;
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return -ENOMEM;
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}
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static int hantro_hevc_validate_sps(struct hantro_ctx *ctx, const struct v4l2_ctrl_hevc_sps *sps)
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{
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/*
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* for tile pixel format check if the width and height match
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* hardware constraints
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*/
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if (ctx->vpu_dst_fmt->fourcc == V4L2_PIX_FMT_NV12_4L4) {
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if (ctx->dst_fmt.width !=
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ALIGN(sps->pic_width_in_luma_samples, ctx->vpu_dst_fmt->frmsize.step_width))
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return -EINVAL;
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if (ctx->dst_fmt.height !=
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ALIGN(sps->pic_height_in_luma_samples, ctx->vpu_dst_fmt->frmsize.step_height))
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return -EINVAL;
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}
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return 0;
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}
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int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx)
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{
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struct hantro_hevc_dec_hw_ctx *hevc_ctx = &ctx->hevc_dec;
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struct hantro_hevc_dec_ctrls *ctrls = &hevc_ctx->ctrls;
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int ret;
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hantro_start_prepare_run(ctx);
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ctrls->decode_params =
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hantro_get_ctrl(ctx, V4L2_CID_STATELESS_HEVC_DECODE_PARAMS);
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if (WARN_ON(!ctrls->decode_params))
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return -EINVAL;
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ctrls->scaling =
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hantro_get_ctrl(ctx, V4L2_CID_STATELESS_HEVC_SCALING_MATRIX);
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if (WARN_ON(!ctrls->scaling))
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return -EINVAL;
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ctrls->sps =
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hantro_get_ctrl(ctx, V4L2_CID_STATELESS_HEVC_SPS);
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if (WARN_ON(!ctrls->sps))
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return -EINVAL;
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ret = hantro_hevc_validate_sps(ctx, ctrls->sps);
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if (ret)
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return ret;
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ctrls->pps =
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hantro_get_ctrl(ctx, V4L2_CID_STATELESS_HEVC_PPS);
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if (WARN_ON(!ctrls->pps))
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return -EINVAL;
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ret = tile_buffer_reallocate(ctx);
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if (ret)
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return ret;
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return 0;
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}
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void hantro_hevc_dec_exit(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
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if (hevc_dec->tile_sizes.cpu)
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dma_free_coherent(vpu->dev, hevc_dec->tile_sizes.size,
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hevc_dec->tile_sizes.cpu,
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hevc_dec->tile_sizes.dma);
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hevc_dec->tile_sizes.cpu = NULL;
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if (hevc_dec->scaling_lists.cpu)
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dma_free_coherent(vpu->dev, hevc_dec->scaling_lists.size,
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hevc_dec->scaling_lists.cpu,
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hevc_dec->scaling_lists.dma);
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hevc_dec->scaling_lists.cpu = NULL;
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if (hevc_dec->tile_filter.cpu)
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dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size,
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hevc_dec->tile_filter.cpu,
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hevc_dec->tile_filter.dma);
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hevc_dec->tile_filter.cpu = NULL;
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if (hevc_dec->tile_sao.cpu)
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dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size,
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hevc_dec->tile_sao.cpu,
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hevc_dec->tile_sao.dma);
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hevc_dec->tile_sao.cpu = NULL;
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if (hevc_dec->tile_bsd.cpu)
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dma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size,
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hevc_dec->tile_bsd.cpu,
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hevc_dec->tile_bsd.dma);
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hevc_dec->tile_bsd.cpu = NULL;
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}
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int hantro_hevc_dec_init(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
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unsigned int size;
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memset(hevc_dec, 0, sizeof(*hevc_dec));
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/*
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* Maximum number of tiles times width and height (2 bytes each),
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* rounding up to next 16 bytes boundary + one extra 16 byte
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* chunk (HW guys wanted to have this).
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*/
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size = round_up(MAX_TILE_COLS * MAX_TILE_ROWS * 4 * sizeof(u16) + 16, 16);
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hevc_dec->tile_sizes.cpu = dma_alloc_coherent(vpu->dev, size,
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&hevc_dec->tile_sizes.dma,
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GFP_KERNEL);
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if (!hevc_dec->tile_sizes.cpu)
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return -ENOMEM;
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hevc_dec->tile_sizes.size = size;
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hevc_dec->scaling_lists.cpu = dma_alloc_coherent(vpu->dev, SCALING_LIST_SIZE,
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&hevc_dec->scaling_lists.dma,
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GFP_KERNEL);
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if (!hevc_dec->scaling_lists.cpu)
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return -ENOMEM;
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hevc_dec->scaling_lists.size = SCALING_LIST_SIZE;
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hantro_hevc_ref_init(ctx);
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return 0;
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}
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