319 lines
9.9 KiB
C
319 lines
9.9 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* SN Platform GRU Driver
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*
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* MMUOPS callbacks + TLB flushing
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*
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* This file handles emu notifier callbacks from the core kernel. The callbacks
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* are used to update the TLB in the GRU as a result of changes in the
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* state of a process address space. This file also handles TLB invalidates
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* from the GRU driver.
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*
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* Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/hugetlb.h>
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#include <linux/delay.h>
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#include <linux/timex.h>
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#include <linux/srcu.h>
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#include <asm/processor.h>
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#include "gru.h"
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#include "grutables.h"
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#include <asm/uv/uv_hub.h>
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#define gru_random() get_cycles()
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/* ---------------------------------- TLB Invalidation functions --------
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* get_tgh_handle
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*
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* Find a TGH to use for issuing a TLB invalidate. For GRUs that are on the
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* local blade, use a fixed TGH that is a function of the blade-local cpu
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* number. Normally, this TGH is private to the cpu & no contention occurs for
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* the TGH. For offblade GRUs, select a random TGH in the range above the
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* private TGHs. A spinlock is required to access this TGH & the lock must be
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* released when the invalidate is completes. This sucks, but it is the best we
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* can do.
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*
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* Note that the spinlock is IN the TGH handle so locking does not involve
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* additional cache lines.
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*
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*/
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static inline int get_off_blade_tgh(struct gru_state *gru)
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{
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int n;
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n = GRU_NUM_TGH - gru->gs_tgh_first_remote;
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n = gru_random() % n;
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n += gru->gs_tgh_first_remote;
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return n;
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}
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static inline int get_on_blade_tgh(struct gru_state *gru)
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{
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return uv_blade_processor_id() >> gru->gs_tgh_local_shift;
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}
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static struct gru_tlb_global_handle *get_lock_tgh_handle(struct gru_state
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*gru)
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{
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struct gru_tlb_global_handle *tgh;
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int n;
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preempt_disable();
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if (uv_numa_blade_id() == gru->gs_blade_id)
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n = get_on_blade_tgh(gru);
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else
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n = get_off_blade_tgh(gru);
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tgh = get_tgh_by_index(gru, n);
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lock_tgh_handle(tgh);
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return tgh;
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}
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static void get_unlock_tgh_handle(struct gru_tlb_global_handle *tgh)
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{
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unlock_tgh_handle(tgh);
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preempt_enable();
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}
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/*
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* gru_flush_tlb_range
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*
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* General purpose TLB invalidation function. This function scans every GRU in
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* the ENTIRE system (partition) looking for GRUs where the specified MM has
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* been accessed by the GRU. For each GRU found, the TLB must be invalidated OR
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* the ASID invalidated. Invalidating an ASID causes a new ASID to be assigned
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* on the next fault. This effectively flushes the ENTIRE TLB for the MM at the
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* cost of (possibly) a large number of future TLBmisses.
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*
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* The current algorithm is optimized based on the following (somewhat true)
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* assumptions:
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* - GRU contexts are not loaded into a GRU unless a reference is made to
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* the data segment or control block (this is true, not an assumption).
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* If a DS/CB is referenced, the user will also issue instructions that
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* cause TLBmisses. It is not necessary to optimize for the case where
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* contexts are loaded but no instructions cause TLB misses. (I know
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* this will happen but I'm not optimizing for it).
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* - GRU instructions to invalidate TLB entries are SLOOOOWWW - normally
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* a few usec but in unusual cases, it could be longer. Avoid if
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* possible.
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* - intrablade process migration between cpus is not frequent but is
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* common.
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* - a GRU context is not typically migrated to a different GRU on the
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* blade because of intrablade migration
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* - interblade migration is rare. Processes migrate their GRU context to
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* the new blade.
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* - if interblade migration occurs, migration back to the original blade
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* is very very rare (ie., no optimization for this case)
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* - most GRU instruction operate on a subset of the user REGIONS. Code
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* & shared library regions are not likely targets of GRU instructions.
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*
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* To help improve the efficiency of TLB invalidation, the GMS data
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* structure is maintained for EACH address space (MM struct). The GMS is
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* also the structure that contains the pointer to the mmu callout
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* functions. This structure is linked to the mm_struct for the address space
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* using the mmu "register" function. The mmu interfaces are used to
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* provide the callbacks for TLB invalidation. The GMS contains:
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*
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* - asid[maxgrus] array. ASIDs are assigned to a GRU when a context is
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* loaded into the GRU.
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* - asidmap[maxgrus]. bitmap to make it easier to find non-zero asids in
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* the above array
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* - ctxbitmap[maxgrus]. Indicates the contexts that are currently active
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* in the GRU for the address space. This bitmap must be passed to the
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* GRU to do an invalidate.
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*
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* The current algorithm for invalidating TLBs is:
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* - scan the asidmap for GRUs where the context has been loaded, ie,
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* asid is non-zero.
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* - for each gru found:
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* - if the ctxtmap is non-zero, there are active contexts in the
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* GRU. TLB invalidate instructions must be issued to the GRU.
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* - if the ctxtmap is zero, no context is active. Set the ASID to
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* zero to force a full TLB invalidation. This is fast but will
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* cause a lot of TLB misses if the context is reloaded onto the
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* GRU
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*
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*/
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void gru_flush_tlb_range(struct gru_mm_struct *gms, unsigned long start,
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unsigned long len)
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{
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struct gru_state *gru;
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struct gru_mm_tracker *asids;
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struct gru_tlb_global_handle *tgh;
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unsigned long num;
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int grupagesize, pagesize, pageshift, gid, asid;
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/* ZZZ TODO - handle huge pages */
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pageshift = PAGE_SHIFT;
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pagesize = (1UL << pageshift);
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grupagesize = GRU_PAGESIZE(pageshift);
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num = min(((len + pagesize - 1) >> pageshift), GRUMAXINVAL);
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STAT(flush_tlb);
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gru_dbg(grudev, "gms %p, start 0x%lx, len 0x%lx, asidmap 0x%lx\n", gms,
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start, len, gms->ms_asidmap[0]);
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spin_lock(&gms->ms_asid_lock);
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for_each_gru_in_bitmap(gid, gms->ms_asidmap) {
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STAT(flush_tlb_gru);
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gru = GID_TO_GRU(gid);
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asids = gms->ms_asids + gid;
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asid = asids->mt_asid;
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if (asids->mt_ctxbitmap && asid) {
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STAT(flush_tlb_gru_tgh);
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asid = GRUASID(asid, start);
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gru_dbg(grudev,
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" FLUSH gruid %d, asid 0x%x, vaddr 0x%lx, vamask 0x%x, num %ld, cbmap 0x%x\n",
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gid, asid, start, grupagesize, num, asids->mt_ctxbitmap);
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tgh = get_lock_tgh_handle(gru);
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tgh_invalidate(tgh, start, ~0, asid, grupagesize, 0,
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num - 1, asids->mt_ctxbitmap);
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get_unlock_tgh_handle(tgh);
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} else {
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STAT(flush_tlb_gru_zero_asid);
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asids->mt_asid = 0;
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__clear_bit(gru->gs_gid, gms->ms_asidmap);
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gru_dbg(grudev,
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" CLEARASID gruid %d, asid 0x%x, cbtmap 0x%x, asidmap 0x%lx\n",
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gid, asid, asids->mt_ctxbitmap,
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gms->ms_asidmap[0]);
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}
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}
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spin_unlock(&gms->ms_asid_lock);
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}
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/*
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* Flush the entire TLB on a chiplet.
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*/
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void gru_flush_all_tlb(struct gru_state *gru)
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{
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struct gru_tlb_global_handle *tgh;
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gru_dbg(grudev, "gid %d\n", gru->gs_gid);
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tgh = get_lock_tgh_handle(gru);
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tgh_invalidate(tgh, 0, ~0, 0, 1, 1, GRUMAXINVAL - 1, 0xffff);
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get_unlock_tgh_handle(tgh);
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}
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/*
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* MMUOPS notifier callout functions
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*/
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static int gru_invalidate_range_start(struct mmu_notifier *mn,
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const struct mmu_notifier_range *range)
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{
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struct gru_mm_struct *gms = container_of(mn, struct gru_mm_struct,
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ms_notifier);
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STAT(mmu_invalidate_range);
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atomic_inc(&gms->ms_range_active);
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gru_dbg(grudev, "gms %p, start 0x%lx, end 0x%lx, act %d\n", gms,
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range->start, range->end, atomic_read(&gms->ms_range_active));
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gru_flush_tlb_range(gms, range->start, range->end - range->start);
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return 0;
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}
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static void gru_invalidate_range_end(struct mmu_notifier *mn,
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const struct mmu_notifier_range *range)
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{
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struct gru_mm_struct *gms = container_of(mn, struct gru_mm_struct,
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ms_notifier);
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/* ..._and_test() provides needed barrier */
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(void)atomic_dec_and_test(&gms->ms_range_active);
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wake_up_all(&gms->ms_wait_queue);
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gru_dbg(grudev, "gms %p, start 0x%lx, end 0x%lx\n",
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gms, range->start, range->end);
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}
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static struct mmu_notifier *gru_alloc_notifier(struct mm_struct *mm)
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{
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struct gru_mm_struct *gms;
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gms = kzalloc(sizeof(*gms), GFP_KERNEL);
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if (!gms)
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return ERR_PTR(-ENOMEM);
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STAT(gms_alloc);
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spin_lock_init(&gms->ms_asid_lock);
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init_waitqueue_head(&gms->ms_wait_queue);
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return &gms->ms_notifier;
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}
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static void gru_free_notifier(struct mmu_notifier *mn)
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{
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kfree(container_of(mn, struct gru_mm_struct, ms_notifier));
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STAT(gms_free);
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}
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static const struct mmu_notifier_ops gru_mmuops = {
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.invalidate_range_start = gru_invalidate_range_start,
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.invalidate_range_end = gru_invalidate_range_end,
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.alloc_notifier = gru_alloc_notifier,
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.free_notifier = gru_free_notifier,
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};
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struct gru_mm_struct *gru_register_mmu_notifier(void)
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{
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struct mmu_notifier *mn;
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mn = mmu_notifier_get_locked(&gru_mmuops, current->mm);
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if (IS_ERR(mn))
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return ERR_CAST(mn);
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return container_of(mn, struct gru_mm_struct, ms_notifier);
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}
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void gru_drop_mmu_notifier(struct gru_mm_struct *gms)
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{
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mmu_notifier_put(&gms->ms_notifier);
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}
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/*
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* Setup TGH parameters. There are:
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* - 24 TGH handles per GRU chiplet
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* - a portion (MAX_LOCAL_TGH) of the handles are reserved for
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* use by blade-local cpus
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* - the rest are used by off-blade cpus. This usage is
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* less frequent than blade-local usage.
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*
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* For now, use 16 handles for local flushes, 8 for remote flushes. If the blade
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* has less tan or equal to 16 cpus, each cpu has a unique handle that it can
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* use.
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*/
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#define MAX_LOCAL_TGH 16
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void gru_tgh_flush_init(struct gru_state *gru)
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{
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int cpus, shift = 0, n;
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cpus = uv_blade_nr_possible_cpus(gru->gs_blade_id);
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/* n = cpus rounded up to next power of 2 */
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if (cpus) {
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n = 1 << fls(cpus - 1);
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/*
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* shift count for converting local cpu# to TGH index
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* 0 if cpus <= MAX_LOCAL_TGH,
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* 1 if cpus <= 2*MAX_LOCAL_TGH,
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* etc
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*/
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shift = max(0, fls(n - 1) - fls(MAX_LOCAL_TGH - 1));
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}
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gru->gs_tgh_local_shift = shift;
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/* first starting TGH index to use for remote purges */
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gru->gs_tgh_first_remote = (cpus + (1 << shift) - 1) >> shift;
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}
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