610 lines
16 KiB
C
610 lines
16 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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//
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// mcp251xfd - Microchip MCP251xFD Family CAN controller driver
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//
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// Copyright (c) 2019, 2020, 2021 Pengutronix,
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// Marc Kleine-Budde <kernel@pengutronix.de>
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//
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#include "mcp251xfd.h"
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#include <asm/unaligned.h>
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static const struct regmap_config mcp251xfd_regmap_crc;
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static int
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mcp251xfd_regmap_nocrc_write(void *context, const void *data, size_t count)
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{
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struct spi_device *spi = context;
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return spi_write(spi, data, count);
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}
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static int
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mcp251xfd_regmap_nocrc_gather_write(void *context,
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const void *reg, size_t reg_len,
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const void *val, size_t val_len)
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{
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struct spi_device *spi = context;
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struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
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struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx;
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struct spi_transfer xfer[] = {
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{
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.tx_buf = buf_tx,
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.len = sizeof(buf_tx->cmd) + val_len,
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},
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};
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BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16));
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if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
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reg_len != sizeof(buf_tx->cmd.cmd))
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return -EINVAL;
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memcpy(&buf_tx->cmd, reg, sizeof(buf_tx->cmd));
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memcpy(buf_tx->data, val, val_len);
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return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
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}
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static inline bool
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mcp251xfd_update_bits_read_reg(const struct mcp251xfd_priv *priv,
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unsigned int reg)
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{
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struct mcp251xfd_rx_ring *ring;
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int n;
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switch (reg) {
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case MCP251XFD_REG_INT:
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case MCP251XFD_REG_TEFCON:
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case MCP251XFD_REG_FLTCON(0):
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case MCP251XFD_REG_ECCSTAT:
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case MCP251XFD_REG_CRC:
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return false;
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case MCP251XFD_REG_CON:
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case MCP251XFD_REG_OSC:
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case MCP251XFD_REG_ECCCON:
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return true;
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default:
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mcp251xfd_for_each_rx_ring(priv, ring, n) {
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if (reg == MCP251XFD_REG_FIFOCON(ring->fifo_nr))
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return false;
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if (reg == MCP251XFD_REG_FIFOSTA(ring->fifo_nr))
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return true;
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}
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WARN(1, "Status of reg 0x%04x unknown.\n", reg);
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}
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return true;
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}
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static int
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mcp251xfd_regmap_nocrc_update_bits(void *context, unsigned int reg,
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unsigned int mask, unsigned int val)
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{
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struct spi_device *spi = context;
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struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
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struct mcp251xfd_map_buf_nocrc *buf_rx = priv->map_buf_nocrc_rx;
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struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx;
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__le32 orig_le32 = 0, mask_le32, val_le32, tmp_le32;
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u8 first_byte, last_byte, len;
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int err;
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BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16));
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BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16));
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if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
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mask == 0)
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return -EINVAL;
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first_byte = mcp251xfd_first_byte_set(mask);
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last_byte = mcp251xfd_last_byte_set(mask);
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len = last_byte - first_byte + 1;
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if (mcp251xfd_update_bits_read_reg(priv, reg)) {
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struct spi_transfer xfer[2] = { };
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struct spi_message msg;
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spi_message_init(&msg);
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spi_message_add_tail(&xfer[0], &msg);
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if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) {
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xfer[0].tx_buf = buf_tx;
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xfer[0].len = sizeof(buf_tx->cmd);
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xfer[1].rx_buf = buf_rx->data;
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xfer[1].len = len;
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spi_message_add_tail(&xfer[1], &msg);
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} else {
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xfer[0].tx_buf = buf_tx;
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xfer[0].rx_buf = buf_rx;
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xfer[0].len = sizeof(buf_tx->cmd) + len;
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if (MCP251XFD_SANITIZE_SPI)
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memset(buf_tx->data, 0x0, len);
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}
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mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, reg + first_byte);
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err = spi_sync(spi, &msg);
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if (err)
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return err;
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memcpy(&orig_le32, buf_rx->data, len);
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}
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mask_le32 = cpu_to_le32(mask >> BITS_PER_BYTE * first_byte);
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val_le32 = cpu_to_le32(val >> BITS_PER_BYTE * first_byte);
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tmp_le32 = orig_le32 & ~mask_le32;
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tmp_le32 |= val_le32 & mask_le32;
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mcp251xfd_spi_cmd_write_nocrc(&buf_tx->cmd, reg + first_byte);
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memcpy(buf_tx->data, &tmp_le32, len);
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return spi_write(spi, buf_tx, sizeof(buf_tx->cmd) + len);
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}
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static int
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mcp251xfd_regmap_nocrc_read(void *context,
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const void *reg, size_t reg_len,
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void *val_buf, size_t val_len)
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{
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struct spi_device *spi = context;
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struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
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struct mcp251xfd_map_buf_nocrc *buf_rx = priv->map_buf_nocrc_rx;
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struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx;
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struct spi_transfer xfer[2] = { };
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struct spi_message msg;
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int err;
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BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16));
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BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16));
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if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
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reg_len != sizeof(buf_tx->cmd.cmd))
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return -EINVAL;
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spi_message_init(&msg);
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spi_message_add_tail(&xfer[0], &msg);
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if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) {
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xfer[0].tx_buf = reg;
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xfer[0].len = sizeof(buf_tx->cmd);
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xfer[1].rx_buf = val_buf;
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xfer[1].len = val_len;
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spi_message_add_tail(&xfer[1], &msg);
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} else {
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xfer[0].tx_buf = buf_tx;
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xfer[0].rx_buf = buf_rx;
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xfer[0].len = sizeof(buf_tx->cmd) + val_len;
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memcpy(&buf_tx->cmd, reg, sizeof(buf_tx->cmd));
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if (MCP251XFD_SANITIZE_SPI)
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memset(buf_tx->data, 0x0, val_len);
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}
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err = spi_sync(spi, &msg);
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if (err)
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return err;
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if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX))
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memcpy(val_buf, buf_rx->data, val_len);
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return 0;
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}
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static int
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mcp251xfd_regmap_crc_gather_write(void *context,
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const void *reg_p, size_t reg_len,
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const void *val, size_t val_len)
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{
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struct spi_device *spi = context;
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struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
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struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx;
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struct spi_transfer xfer[] = {
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{
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.tx_buf = buf_tx,
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.len = sizeof(buf_tx->cmd) + val_len +
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sizeof(buf_tx->crc),
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},
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};
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u16 reg = *(u16 *)reg_p;
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u16 crc;
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BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8));
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if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
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reg_len != sizeof(buf_tx->cmd.cmd) +
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mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE)
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return -EINVAL;
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mcp251xfd_spi_cmd_write_crc(&buf_tx->cmd, reg, val_len);
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memcpy(buf_tx->data, val, val_len);
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crc = mcp251xfd_crc16_compute(buf_tx, sizeof(buf_tx->cmd) + val_len);
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put_unaligned_be16(crc, buf_tx->data + val_len);
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return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
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}
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static int
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mcp251xfd_regmap_crc_write(void *context,
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const void *data, size_t count)
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{
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const size_t data_offset = sizeof(__be16) +
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mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE;
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return mcp251xfd_regmap_crc_gather_write(context,
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data, data_offset,
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data + data_offset,
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count - data_offset);
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}
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static int
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mcp251xfd_regmap_crc_read_check_crc(const struct mcp251xfd_map_buf_crc * const buf_rx,
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const struct mcp251xfd_map_buf_crc * const buf_tx,
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unsigned int data_len)
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{
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u16 crc_received, crc_calculated;
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crc_received = get_unaligned_be16(buf_rx->data + data_len);
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crc_calculated = mcp251xfd_crc16_compute2(&buf_tx->cmd,
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sizeof(buf_tx->cmd),
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buf_rx->data,
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data_len);
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if (crc_received != crc_calculated)
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return -EBADMSG;
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return 0;
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}
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static int
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mcp251xfd_regmap_crc_read_one(struct mcp251xfd_priv *priv,
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struct spi_message *msg, unsigned int data_len)
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{
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const struct mcp251xfd_map_buf_crc *buf_rx = priv->map_buf_crc_rx;
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const struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx;
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int err;
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BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16) + sizeof(u8));
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BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8));
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err = spi_sync(priv->spi, msg);
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if (err)
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return err;
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return mcp251xfd_regmap_crc_read_check_crc(buf_rx, buf_tx, data_len);
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}
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static int
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mcp251xfd_regmap_crc_read(void *context,
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const void *reg_p, size_t reg_len,
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void *val_buf, size_t val_len)
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{
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struct spi_device *spi = context;
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struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
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struct mcp251xfd_map_buf_crc *buf_rx = priv->map_buf_crc_rx;
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struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx;
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struct spi_transfer xfer[2] = { };
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struct spi_message msg;
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u16 reg = *(u16 *)reg_p;
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int i, err;
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BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16) + sizeof(u8));
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BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8));
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if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
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reg_len != sizeof(buf_tx->cmd.cmd) +
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mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE)
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return -EINVAL;
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spi_message_init(&msg);
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spi_message_add_tail(&xfer[0], &msg);
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if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) {
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xfer[0].tx_buf = buf_tx;
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xfer[0].len = sizeof(buf_tx->cmd);
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xfer[1].rx_buf = buf_rx->data;
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xfer[1].len = val_len + sizeof(buf_tx->crc);
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spi_message_add_tail(&xfer[1], &msg);
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} else {
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xfer[0].tx_buf = buf_tx;
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xfer[0].rx_buf = buf_rx;
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xfer[0].len = sizeof(buf_tx->cmd) + val_len +
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sizeof(buf_tx->crc);
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if (MCP251XFD_SANITIZE_SPI)
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memset(buf_tx->data, 0x0, val_len +
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sizeof(buf_tx->crc));
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}
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mcp251xfd_spi_cmd_read_crc(&buf_tx->cmd, reg, val_len);
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for (i = 0; i < MCP251XFD_READ_CRC_RETRIES_MAX; i++) {
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err = mcp251xfd_regmap_crc_read_one(priv, &msg, val_len);
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if (!err)
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goto out;
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if (err != -EBADMSG)
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return err;
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/* MCP251XFD_REG_TBC is the time base counter
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* register. It increments once per SYS clock tick,
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* which is 20 or 40 MHz.
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*
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* Observation on the mcp2518fd shows that if the
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* lowest byte (which is transferred first on the SPI
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* bus) of that register is 0x00 or 0x80 the
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* calculated CRC doesn't always match the transferred
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|
|
* one. On the mcp2517fd this problem is not limited
|
||
|
|
* to the first byte being 0x00 or 0x80.
|
||
|
|
*
|
||
|
|
* If the highest bit in the lowest byte is flipped
|
||
|
|
* the transferred CRC matches the calculated one. We
|
||
|
|
* assume for now the CRC operates on the correct
|
||
|
|
* data.
|
||
|
|
*/
|
||
|
|
if (reg == MCP251XFD_REG_TBC &&
|
||
|
|
((buf_rx->data[0] & 0xf8) == 0x0 ||
|
||
|
|
(buf_rx->data[0] & 0xf8) == 0x80)) {
|
||
|
|
/* Flip highest bit in lowest byte of le32 */
|
||
|
|
buf_rx->data[0] ^= 0x80;
|
||
|
|
|
||
|
|
/* re-check CRC */
|
||
|
|
err = mcp251xfd_regmap_crc_read_check_crc(buf_rx,
|
||
|
|
buf_tx,
|
||
|
|
val_len);
|
||
|
|
if (!err) {
|
||
|
|
/* If CRC is now correct, assume
|
||
|
|
* flipped data is OK.
|
||
|
|
*/
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* MCP251XFD_REG_OSC is the first ever reg we read from.
|
||
|
|
*
|
||
|
|
* The chip may be in deep sleep and this SPI transfer
|
||
|
|
* (i.e. the assertion of the CS) will wake the chip
|
||
|
|
* up. This takes about 3ms. The CRC of this transfer
|
||
|
|
* is wrong.
|
||
|
|
*
|
||
|
|
* Or there isn't a chip at all, in this case the CRC
|
||
|
|
* will be wrong, too.
|
||
|
|
*
|
||
|
|
* In both cases ignore the CRC and copy the read data
|
||
|
|
* to the caller. It will take care of both cases.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
if (reg == MCP251XFD_REG_OSC && val_len == sizeof(__le32)) {
|
||
|
|
err = 0;
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
netdev_info(priv->ndev,
|
||
|
|
"CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x) retrying.\n",
|
||
|
|
reg, val_len, (int)val_len, buf_rx->data,
|
||
|
|
get_unaligned_be16(buf_rx->data + val_len));
|
||
|
|
}
|
||
|
|
|
||
|
|
if (err) {
|
||
|
|
netdev_err(priv->ndev,
|
||
|
|
"CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x).\n",
|
||
|
|
reg, val_len, (int)val_len, buf_rx->data,
|
||
|
|
get_unaligned_be16(buf_rx->data + val_len));
|
||
|
|
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
out:
|
||
|
|
memcpy(val_buf, buf_rx->data, val_len);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct regmap_range mcp251xfd_reg_table_yes_range[] = {
|
||
|
|
regmap_reg_range(0x000, 0x2ec), /* CAN FD Controller Module SFR */
|
||
|
|
regmap_reg_range(0x400, 0xbfc), /* RAM */
|
||
|
|
regmap_reg_range(0xe00, 0xe14), /* MCP2517/18FD SFR */
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct regmap_access_table mcp251xfd_reg_table = {
|
||
|
|
.yes_ranges = mcp251xfd_reg_table_yes_range,
|
||
|
|
.n_yes_ranges = ARRAY_SIZE(mcp251xfd_reg_table_yes_range),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct regmap_config mcp251xfd_regmap_nocrc = {
|
||
|
|
.name = "nocrc",
|
||
|
|
.reg_bits = 16,
|
||
|
|
.reg_stride = 4,
|
||
|
|
.pad_bits = 0,
|
||
|
|
.val_bits = 32,
|
||
|
|
.max_register = 0xffc,
|
||
|
|
.wr_table = &mcp251xfd_reg_table,
|
||
|
|
.rd_table = &mcp251xfd_reg_table,
|
||
|
|
.cache_type = REGCACHE_NONE,
|
||
|
|
.read_flag_mask = (__force unsigned long)
|
||
|
|
cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_READ),
|
||
|
|
.write_flag_mask = (__force unsigned long)
|
||
|
|
cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_WRITE),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct regmap_bus mcp251xfd_bus_nocrc = {
|
||
|
|
.write = mcp251xfd_regmap_nocrc_write,
|
||
|
|
.gather_write = mcp251xfd_regmap_nocrc_gather_write,
|
||
|
|
.reg_update_bits = mcp251xfd_regmap_nocrc_update_bits,
|
||
|
|
.read = mcp251xfd_regmap_nocrc_read,
|
||
|
|
.reg_format_endian_default = REGMAP_ENDIAN_BIG,
|
||
|
|
.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
|
||
|
|
.max_raw_read = sizeof_field(struct mcp251xfd_map_buf_nocrc, data),
|
||
|
|
.max_raw_write = sizeof_field(struct mcp251xfd_map_buf_nocrc, data),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct regmap_config mcp251xfd_regmap_crc = {
|
||
|
|
.name = "crc",
|
||
|
|
.reg_bits = 16,
|
||
|
|
.reg_stride = 4,
|
||
|
|
.pad_bits = 16, /* keep data bits aligned */
|
||
|
|
.val_bits = 32,
|
||
|
|
.max_register = 0xffc,
|
||
|
|
.wr_table = &mcp251xfd_reg_table,
|
||
|
|
.rd_table = &mcp251xfd_reg_table,
|
||
|
|
.cache_type = REGCACHE_NONE,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct regmap_bus mcp251xfd_bus_crc = {
|
||
|
|
.write = mcp251xfd_regmap_crc_write,
|
||
|
|
.gather_write = mcp251xfd_regmap_crc_gather_write,
|
||
|
|
.read = mcp251xfd_regmap_crc_read,
|
||
|
|
.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
|
||
|
|
.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
|
||
|
|
.max_raw_read = sizeof_field(struct mcp251xfd_map_buf_crc, data),
|
||
|
|
.max_raw_write = sizeof_field(struct mcp251xfd_map_buf_crc, data),
|
||
|
|
};
|
||
|
|
|
||
|
|
static inline bool
|
||
|
|
mcp251xfd_regmap_use_nocrc(struct mcp251xfd_priv *priv)
|
||
|
|
{
|
||
|
|
return (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG)) ||
|
||
|
|
(!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX));
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool
|
||
|
|
mcp251xfd_regmap_use_crc(struct mcp251xfd_priv *priv)
|
||
|
|
{
|
||
|
|
return (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG) ||
|
||
|
|
(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
mcp251xfd_regmap_init_nocrc(struct mcp251xfd_priv *priv)
|
||
|
|
{
|
||
|
|
if (!priv->map_nocrc) {
|
||
|
|
struct regmap *map;
|
||
|
|
|
||
|
|
map = devm_regmap_init(&priv->spi->dev, &mcp251xfd_bus_nocrc,
|
||
|
|
priv->spi, &mcp251xfd_regmap_nocrc);
|
||
|
|
if (IS_ERR(map))
|
||
|
|
return PTR_ERR(map);
|
||
|
|
|
||
|
|
priv->map_nocrc = map;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!priv->map_buf_nocrc_rx) {
|
||
|
|
priv->map_buf_nocrc_rx =
|
||
|
|
devm_kzalloc(&priv->spi->dev,
|
||
|
|
sizeof(*priv->map_buf_nocrc_rx),
|
||
|
|
GFP_KERNEL);
|
||
|
|
if (!priv->map_buf_nocrc_rx)
|
||
|
|
return -ENOMEM;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!priv->map_buf_nocrc_tx) {
|
||
|
|
priv->map_buf_nocrc_tx =
|
||
|
|
devm_kzalloc(&priv->spi->dev,
|
||
|
|
sizeof(*priv->map_buf_nocrc_tx),
|
||
|
|
GFP_KERNEL);
|
||
|
|
if (!priv->map_buf_nocrc_tx)
|
||
|
|
return -ENOMEM;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG))
|
||
|
|
priv->map_reg = priv->map_nocrc;
|
||
|
|
|
||
|
|
if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX))
|
||
|
|
priv->map_rx = priv->map_nocrc;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void mcp251xfd_regmap_destroy_nocrc(struct mcp251xfd_priv *priv)
|
||
|
|
{
|
||
|
|
if (priv->map_buf_nocrc_rx) {
|
||
|
|
devm_kfree(&priv->spi->dev, priv->map_buf_nocrc_rx);
|
||
|
|
priv->map_buf_nocrc_rx = NULL;
|
||
|
|
}
|
||
|
|
if (priv->map_buf_nocrc_tx) {
|
||
|
|
devm_kfree(&priv->spi->dev, priv->map_buf_nocrc_tx);
|
||
|
|
priv->map_buf_nocrc_tx = NULL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
mcp251xfd_regmap_init_crc(struct mcp251xfd_priv *priv)
|
||
|
|
{
|
||
|
|
if (!priv->map_crc) {
|
||
|
|
struct regmap *map;
|
||
|
|
|
||
|
|
map = devm_regmap_init(&priv->spi->dev, &mcp251xfd_bus_crc,
|
||
|
|
priv->spi, &mcp251xfd_regmap_crc);
|
||
|
|
if (IS_ERR(map))
|
||
|
|
return PTR_ERR(map);
|
||
|
|
|
||
|
|
priv->map_crc = map;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!priv->map_buf_crc_rx) {
|
||
|
|
priv->map_buf_crc_rx =
|
||
|
|
devm_kzalloc(&priv->spi->dev,
|
||
|
|
sizeof(*priv->map_buf_crc_rx),
|
||
|
|
GFP_KERNEL);
|
||
|
|
if (!priv->map_buf_crc_rx)
|
||
|
|
return -ENOMEM;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!priv->map_buf_crc_tx) {
|
||
|
|
priv->map_buf_crc_tx =
|
||
|
|
devm_kzalloc(&priv->spi->dev,
|
||
|
|
sizeof(*priv->map_buf_crc_tx),
|
||
|
|
GFP_KERNEL);
|
||
|
|
if (!priv->map_buf_crc_tx)
|
||
|
|
return -ENOMEM;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG)
|
||
|
|
priv->map_reg = priv->map_crc;
|
||
|
|
|
||
|
|
if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX)
|
||
|
|
priv->map_rx = priv->map_crc;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void mcp251xfd_regmap_destroy_crc(struct mcp251xfd_priv *priv)
|
||
|
|
{
|
||
|
|
if (priv->map_buf_crc_rx) {
|
||
|
|
devm_kfree(&priv->spi->dev, priv->map_buf_crc_rx);
|
||
|
|
priv->map_buf_crc_rx = NULL;
|
||
|
|
}
|
||
|
|
if (priv->map_buf_crc_tx) {
|
||
|
|
devm_kfree(&priv->spi->dev, priv->map_buf_crc_tx);
|
||
|
|
priv->map_buf_crc_tx = NULL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int mcp251xfd_regmap_init(struct mcp251xfd_priv *priv)
|
||
|
|
{
|
||
|
|
int err;
|
||
|
|
|
||
|
|
if (mcp251xfd_regmap_use_nocrc(priv)) {
|
||
|
|
err = mcp251xfd_regmap_init_nocrc(priv);
|
||
|
|
|
||
|
|
if (err)
|
||
|
|
return err;
|
||
|
|
} else {
|
||
|
|
mcp251xfd_regmap_destroy_nocrc(priv);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (mcp251xfd_regmap_use_crc(priv)) {
|
||
|
|
err = mcp251xfd_regmap_init_crc(priv);
|
||
|
|
|
||
|
|
if (err)
|
||
|
|
return err;
|
||
|
|
} else {
|
||
|
|
mcp251xfd_regmap_destroy_crc(priv);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|