155 lines
4.6 KiB
C
155 lines
4.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013-2014 Chelsio Communications. All rights reserved.
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*
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* Written by Anish Bhatt (anish@chelsio.com)
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*/
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#ifndef __CXGB4_DCB_H
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#define __CXGB4_DCB_H
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#include <linux/netdevice.h>
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#include <linux/dcbnl.h>
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#include <net/dcbnl.h>
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#ifdef CONFIG_CHELSIO_T4_DCB
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#define CXGB4_DCBX_FW_SUPPORT \
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(DCB_CAP_DCBX_VER_CEE | \
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DCB_CAP_DCBX_VER_IEEE | \
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DCB_CAP_DCBX_LLD_MANAGED)
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#define CXGB4_DCBX_HOST_SUPPORT \
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(DCB_CAP_DCBX_VER_CEE | \
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DCB_CAP_DCBX_VER_IEEE | \
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DCB_CAP_DCBX_HOST)
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#define CXGB4_MAX_PRIORITY CXGB4_MAX_DCBX_APP_SUPPORTED
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#define CXGB4_MAX_TCS CXGB4_MAX_DCBX_APP_SUPPORTED
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#define INIT_PORT_DCB_CMD(__pcmd, __port, __op, __action) \
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do { \
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memset(&(__pcmd), 0, sizeof(__pcmd)); \
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(__pcmd).op_to_portid = \
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cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | \
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FW_CMD_REQUEST_F | \
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FW_CMD_##__op##_F | \
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FW_PORT_CMD_PORTID_V(__port)); \
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(__pcmd).action_to_len16 = \
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cpu_to_be32(FW_PORT_CMD_ACTION_V(__action) | \
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FW_LEN16(pcmd)); \
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} while (0)
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#define INIT_PORT_DCB_READ_PEER_CMD(__pcmd, __port) \
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INIT_PORT_DCB_CMD(__pcmd, __port, READ, FW_PORT_ACTION_DCB_READ_RECV)
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#define INIT_PORT_DCB_READ_LOCAL_CMD(__pcmd, __port) \
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INIT_PORT_DCB_CMD(__pcmd, __port, READ, FW_PORT_ACTION_DCB_READ_TRANS)
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#define INIT_PORT_DCB_READ_SYNC_CMD(__pcmd, __port) \
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INIT_PORT_DCB_CMD(__pcmd, __port, READ, FW_PORT_ACTION_DCB_READ_DET)
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#define INIT_PORT_DCB_WRITE_CMD(__pcmd, __port) \
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INIT_PORT_DCB_CMD(__pcmd, __port, EXEC, FW_PORT_ACTION_L2_DCB_CFG)
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#define IEEE_FAUX_SYNC(__dev, __dcb) \
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do { \
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if ((__dcb)->dcb_version == FW_PORT_DCB_VER_IEEE) \
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cxgb4_dcb_state_fsm((__dev), \
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CXGB4_DCB_INPUT_FW_ALLSYNCED); \
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} while (0)
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/* States we can be in for a port's Data Center Bridging.
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*/
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enum cxgb4_dcb_state {
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CXGB4_DCB_STATE_START, /* initial unknown state */
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CXGB4_DCB_STATE_HOST, /* we're using Host DCB (if at all) */
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CXGB4_DCB_STATE_FW_INCOMPLETE, /* using firmware DCB, incomplete */
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CXGB4_DCB_STATE_FW_ALLSYNCED, /* using firmware DCB, all sync'ed */
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};
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/* Data Center Bridging state input for the Finite State Machine.
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*/
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enum cxgb4_dcb_state_input {
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/* Input from the firmware.
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*/
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CXGB4_DCB_INPUT_FW_DISABLED, /* firmware DCB disabled */
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CXGB4_DCB_INPUT_FW_ENABLED, /* firmware DCB enabled */
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CXGB4_DCB_INPUT_FW_INCOMPLETE, /* firmware reports incomplete DCB */
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CXGB4_DCB_INPUT_FW_ALLSYNCED, /* firmware reports all sync'ed */
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};
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/* Firmware DCB messages that we've received so far ...
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*/
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enum cxgb4_dcb_fw_msgs {
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CXGB4_DCB_FW_PGID = 0x01,
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CXGB4_DCB_FW_PGRATE = 0x02,
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CXGB4_DCB_FW_PRIORATE = 0x04,
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CXGB4_DCB_FW_PFC = 0x08,
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CXGB4_DCB_FW_APP_ID = 0x10,
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};
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#define CXGB4_MAX_DCBX_APP_SUPPORTED 8
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/* Data Center Bridging support;
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*/
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struct port_dcb_info {
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enum cxgb4_dcb_state state; /* DCB State Machine */
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enum cxgb4_dcb_fw_msgs msgs; /* DCB Firmware messages received */
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unsigned int supported; /* OS DCB capabilities supported */
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bool enabled; /* OS Enabled state */
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/* Cached copies of DCB information sent by the firmware (in Host
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* Native Endian format).
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*/
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u32 pgid; /* Priority Group[0..7] */
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u8 dcb_version; /* Running DCBx version */
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u8 pfcen; /* Priority Flow Control[0..7] */
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u8 pg_num_tcs_supported; /* max PG Traffic Classes */
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u8 pfc_num_tcs_supported; /* max PFC Traffic Classes */
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u8 pgrate[8]; /* Priority Group Rate[0..7] */
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u8 priorate[8]; /* Priority Rate[0..7] */
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u8 tsa[8]; /* TSA Algorithm[0..7] */
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struct app_priority { /* Application Information */
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u8 user_prio_map; /* Priority Map bitfield */
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u8 sel_field; /* Protocol ID interpretation */
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u16 protocolid; /* Protocol ID */
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} app_priority[CXGB4_MAX_DCBX_APP_SUPPORTED];
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};
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void cxgb4_dcb_state_init(struct net_device *);
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void cxgb4_dcb_version_init(struct net_device *);
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void cxgb4_dcb_reset(struct net_device *dev);
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void cxgb4_dcb_state_fsm(struct net_device *, enum cxgb4_dcb_state_input);
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void cxgb4_dcb_handle_fw_update(struct adapter *, const struct fw_port_cmd *);
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void cxgb4_dcb_set_caps(struct adapter *, const struct fw_port_cmd *);
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extern const struct dcbnl_rtnl_ops cxgb4_dcb_ops;
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static inline __u8 bitswap_1(unsigned char val)
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{
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return ((val & 0x80) >> 7) |
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((val & 0x40) >> 5) |
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((val & 0x20) >> 3) |
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((val & 0x10) >> 1) |
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((val & 0x08) << 1) |
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((val & 0x04) << 3) |
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((val & 0x02) << 5) |
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((val & 0x01) << 7);
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}
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extern const char * const dcb_ver_array[];
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#define CXGB4_DCB_ENABLED true
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#else /* !CONFIG_CHELSIO_T4_DCB */
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static inline void cxgb4_dcb_state_init(struct net_device *dev)
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{
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}
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#define CXGB4_DCB_ENABLED false
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#endif /* !CONFIG_CHELSIO_T4_DCB */
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#endif /* __CXGB4_DCB_H */
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