31 lines
909 B
C
31 lines
909 B
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2020 Intel Corporation */
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bool igc_reg_test(struct igc_adapter *adapter, u64 *data);
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bool igc_eeprom_test(struct igc_adapter *adapter, u64 *data);
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bool igc_link_test(struct igc_adapter *adapter, u64 *data);
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struct igc_reg_test {
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u16 reg;
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u8 array_len;
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u8 test_type;
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u32 mask;
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u32 write;
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};
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/* In the hardware, registers are laid out either singly, in arrays
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* spaced 0x40 bytes apart, or in contiguous tables. We assume
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* most tests take place on arrays or single registers (handled
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* as a single-element array) and special-case the tables.
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* Table tests are always pattern tests.
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*
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* We also make provision for some required setup steps by specifying
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* registers to be written without any read-back testing.
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*/
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#define PATTERN_TEST 1
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#define SET_READ_TEST 2
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#define TABLE32_TEST 3
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#define TABLE64_TEST_LO 4
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#define TABLE64_TEST_HI 5
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