502 lines
15 KiB
C
502 lines
15 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 1999 - 2018 Intel Corporation. */
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#ifndef _IXGBEVF_H_
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#define _IXGBEVF_H_
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include <linux/timer.h>
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#include <linux/io.h>
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#include <linux/netdevice.h>
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#include <linux/if_vlan.h>
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#include <linux/u64_stats_sync.h>
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#include <net/xdp.h>
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#include "vf.h"
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#include "ipsec.h"
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#define IXGBE_MAX_TXD_PWR 14
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#define IXGBE_MAX_DATA_PER_TXD BIT(IXGBE_MAX_TXD_PWR)
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/* Tx Descriptors needed, worst case */
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#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
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#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
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/* wrapper around a pointer to a socket buffer,
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* so a DMA handle can be stored along with the buffer
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*/
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struct ixgbevf_tx_buffer {
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union ixgbe_adv_tx_desc *next_to_watch;
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unsigned long time_stamp;
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union {
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struct sk_buff *skb;
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/* XDP uses address ptr on irq_clean */
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void *data;
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};
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unsigned int bytecount;
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unsigned short gso_segs;
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__be16 protocol;
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DEFINE_DMA_UNMAP_ADDR(dma);
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DEFINE_DMA_UNMAP_LEN(len);
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u32 tx_flags;
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};
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struct ixgbevf_rx_buffer {
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dma_addr_t dma;
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struct page *page;
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#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
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__u32 page_offset;
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#else
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__u16 page_offset;
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#endif
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__u16 pagecnt_bias;
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};
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struct ixgbevf_stats {
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u64 packets;
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u64 bytes;
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};
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struct ixgbevf_tx_queue_stats {
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u64 restart_queue;
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u64 tx_busy;
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u64 tx_done_old;
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};
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struct ixgbevf_rx_queue_stats {
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u64 alloc_rx_page_failed;
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u64 alloc_rx_buff_failed;
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u64 alloc_rx_page;
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u64 csum_err;
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};
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enum ixgbevf_ring_state_t {
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__IXGBEVF_RX_3K_BUFFER,
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__IXGBEVF_RX_BUILD_SKB_ENABLED,
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__IXGBEVF_TX_DETECT_HANG,
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__IXGBEVF_HANG_CHECK_ARMED,
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__IXGBEVF_TX_XDP_RING,
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__IXGBEVF_TX_XDP_RING_PRIMED,
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};
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#define ring_is_xdp(ring) \
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test_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state)
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#define set_ring_xdp(ring) \
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set_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state)
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#define clear_ring_xdp(ring) \
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clear_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state)
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struct ixgbevf_ring {
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struct ixgbevf_ring *next;
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struct ixgbevf_q_vector *q_vector; /* backpointer to q_vector */
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struct net_device *netdev;
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struct bpf_prog *xdp_prog;
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struct device *dev;
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void *desc; /* descriptor ring memory */
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dma_addr_t dma; /* phys. address of descriptor ring */
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unsigned int size; /* length in bytes */
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u16 count; /* amount of descriptors */
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u16 next_to_use;
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u16 next_to_clean;
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u16 next_to_alloc;
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union {
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struct ixgbevf_tx_buffer *tx_buffer_info;
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struct ixgbevf_rx_buffer *rx_buffer_info;
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};
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unsigned long state;
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struct ixgbevf_stats stats;
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struct u64_stats_sync syncp;
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union {
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struct ixgbevf_tx_queue_stats tx_stats;
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struct ixgbevf_rx_queue_stats rx_stats;
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};
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struct xdp_rxq_info xdp_rxq;
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u64 hw_csum_rx_error;
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u8 __iomem *tail;
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struct sk_buff *skb;
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/* holds the special value that gets the hardware register offset
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* associated with this ring, which is different for DCB and RSS modes
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*/
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u16 reg_idx;
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int queue_index; /* needed for multiqueue queue management */
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} ____cacheline_internodealigned_in_smp;
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/* How many Rx Buffers do we bundle into one write to the hardware ? */
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#define IXGBEVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */
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#define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES
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#define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES
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#define MAX_XDP_QUEUES IXGBE_VF_MAX_TX_QUEUES
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#define IXGBEVF_MAX_RSS_QUEUES 2
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#define IXGBEVF_82599_RETA_SIZE 128 /* 128 entries */
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#define IXGBEVF_X550_VFRETA_SIZE 64 /* 64 entries */
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#define IXGBEVF_RSS_HASH_KEY_SIZE 40
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#define IXGBEVF_VFRSSRK_REGS 10 /* 10 registers for RSS key */
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#define IXGBEVF_DEFAULT_TXD 1024
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#define IXGBEVF_DEFAULT_RXD 512
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#define IXGBEVF_MAX_TXD 4096
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#define IXGBEVF_MIN_TXD 64
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#define IXGBEVF_MAX_RXD 4096
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#define IXGBEVF_MIN_RXD 64
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/* Supported Rx Buffer Sizes */
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#define IXGBEVF_RXBUFFER_256 256 /* Used for packet split */
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#define IXGBEVF_RXBUFFER_2048 2048
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#define IXGBEVF_RXBUFFER_3072 3072
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#define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256
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#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
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#define IXGBEVF_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
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#if (PAGE_SIZE < 8192)
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#define IXGBEVF_MAX_FRAME_BUILD_SKB \
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(SKB_WITH_OVERHEAD(IXGBEVF_RXBUFFER_2048) - IXGBEVF_SKB_PAD)
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#else
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#define IXGBEVF_MAX_FRAME_BUILD_SKB IXGBEVF_RXBUFFER_2048
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#endif
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#define IXGBE_TX_FLAGS_CSUM BIT(0)
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#define IXGBE_TX_FLAGS_VLAN BIT(1)
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#define IXGBE_TX_FLAGS_TSO BIT(2)
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#define IXGBE_TX_FLAGS_IPV4 BIT(3)
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#define IXGBE_TX_FLAGS_IPSEC BIT(4)
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#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
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#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
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#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
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#define ring_uses_large_buffer(ring) \
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test_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state)
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#define set_ring_uses_large_buffer(ring) \
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set_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state)
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#define clear_ring_uses_large_buffer(ring) \
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clear_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state)
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#define ring_uses_build_skb(ring) \
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test_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state)
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#define set_ring_build_skb_enabled(ring) \
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set_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state)
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#define clear_ring_build_skb_enabled(ring) \
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clear_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state)
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static inline unsigned int ixgbevf_rx_bufsz(struct ixgbevf_ring *ring)
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{
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#if (PAGE_SIZE < 8192)
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if (ring_uses_large_buffer(ring))
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return IXGBEVF_RXBUFFER_3072;
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if (ring_uses_build_skb(ring))
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return IXGBEVF_MAX_FRAME_BUILD_SKB;
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#endif
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return IXGBEVF_RXBUFFER_2048;
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}
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static inline unsigned int ixgbevf_rx_pg_order(struct ixgbevf_ring *ring)
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{
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#if (PAGE_SIZE < 8192)
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if (ring_uses_large_buffer(ring))
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return 1;
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#endif
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return 0;
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}
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#define ixgbevf_rx_pg_size(_ring) (PAGE_SIZE << ixgbevf_rx_pg_order(_ring))
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#define check_for_tx_hang(ring) \
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test_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
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#define set_check_for_tx_hang(ring) \
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set_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
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#define clear_check_for_tx_hang(ring) \
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clear_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
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struct ixgbevf_ring_container {
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struct ixgbevf_ring *ring; /* pointer to linked list of rings */
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unsigned int total_bytes; /* total bytes processed this int */
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unsigned int total_packets; /* total packets processed this int */
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u8 count; /* total number of rings in vector */
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u8 itr; /* current ITR setting for ring */
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};
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/* iterator for handling rings in ring container */
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#define ixgbevf_for_each_ring(pos, head) \
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for (pos = (head).ring; pos != NULL; pos = pos->next)
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/* MAX_MSIX_Q_VECTORS of these are allocated,
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* but we only use one per queue-specific vector.
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*/
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struct ixgbevf_q_vector {
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struct ixgbevf_adapter *adapter;
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/* index of q_vector within array, also used for finding the bit in
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* EICR and friends that represents the vector for this ring
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*/
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u16 v_idx;
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u16 itr; /* Interrupt throttle rate written to EITR */
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struct napi_struct napi;
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struct ixgbevf_ring_container rx, tx;
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struct rcu_head rcu; /* to avoid race with update stats on free */
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char name[IFNAMSIZ + 9];
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/* for dynamic allocation of rings associated with this q_vector */
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struct ixgbevf_ring ring[0] ____cacheline_internodealigned_in_smp;
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#ifdef CONFIG_NET_RX_BUSY_POLL
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unsigned int state;
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#define IXGBEVF_QV_STATE_IDLE 0
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#define IXGBEVF_QV_STATE_NAPI 1 /* NAPI owns this QV */
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#define IXGBEVF_QV_STATE_POLL 2 /* poll owns this QV */
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#define IXGBEVF_QV_STATE_DISABLED 4 /* QV is disabled */
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#define IXGBEVF_QV_OWNED (IXGBEVF_QV_STATE_NAPI | IXGBEVF_QV_STATE_POLL)
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#define IXGBEVF_QV_LOCKED (IXGBEVF_QV_OWNED | IXGBEVF_QV_STATE_DISABLED)
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#define IXGBEVF_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */
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#define IXGBEVF_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */
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#define IXGBEVF_QV_YIELD (IXGBEVF_QV_STATE_NAPI_YIELD | \
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IXGBEVF_QV_STATE_POLL_YIELD)
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#define IXGBEVF_QV_USER_PEND (IXGBEVF_QV_STATE_POLL | \
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IXGBEVF_QV_STATE_POLL_YIELD)
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spinlock_t lock;
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#endif /* CONFIG_NET_RX_BUSY_POLL */
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};
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/* microsecond values for various ITR rates shifted by 2 to fit itr register
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* with the first 3 bits reserved 0
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*/
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#define IXGBE_MIN_RSC_ITR 24
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#define IXGBE_100K_ITR 40
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#define IXGBE_20K_ITR 200
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#define IXGBE_12K_ITR 336
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/* Helper macros to switch between ints/sec and what the register uses.
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* And yes, it's the same math going both ways. The lowest value
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* supported by all of the ixgbe hardware is 8.
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*/
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#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
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((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
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#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
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/* ixgbevf_test_staterr - tests bits in Rx descriptor status and error fields */
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static inline __le32 ixgbevf_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
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const u32 stat_err_bits)
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{
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return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
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}
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static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring)
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{
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u16 ntc = ring->next_to_clean;
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u16 ntu = ring->next_to_use;
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return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
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}
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static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value)
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{
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writel(value, ring->tail);
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}
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#define IXGBEVF_RX_DESC(R, i) \
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(&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
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#define IXGBEVF_TX_DESC(R, i) \
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(&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
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#define IXGBEVF_TX_CTXTDESC(R, i) \
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(&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
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#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
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#define OTHER_VECTOR 1
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#define NON_Q_VECTORS (OTHER_VECTOR)
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#define MAX_MSIX_Q_VECTORS 2
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#define MIN_MSIX_Q_VECTORS 1
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#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
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#define IXGBEVF_RX_DMA_ATTR \
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(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
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/* board specific private data structure */
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struct ixgbevf_adapter {
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/* this field must be first, see ixgbevf_process_skb_fields */
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unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
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struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
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/* Interrupt Throttle Rate */
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u16 rx_itr_setting;
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u16 tx_itr_setting;
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|
|
/* interrupt masks */
|
||
|
|
u32 eims_enable_mask;
|
||
|
|
u32 eims_other;
|
||
|
|
|
||
|
|
/* XDP */
|
||
|
|
int num_xdp_queues;
|
||
|
|
struct ixgbevf_ring *xdp_ring[MAX_XDP_QUEUES];
|
||
|
|
|
||
|
|
/* TX */
|
||
|
|
int num_tx_queues;
|
||
|
|
struct ixgbevf_ring *tx_ring[MAX_TX_QUEUES]; /* One per active queue */
|
||
|
|
u64 restart_queue;
|
||
|
|
u32 tx_timeout_count;
|
||
|
|
u64 tx_ipsec;
|
||
|
|
|
||
|
|
/* RX */
|
||
|
|
int num_rx_queues;
|
||
|
|
struct ixgbevf_ring *rx_ring[MAX_TX_QUEUES]; /* One per active queue */
|
||
|
|
u64 hw_csum_rx_error;
|
||
|
|
u64 hw_rx_no_dma_resources;
|
||
|
|
int num_msix_vectors;
|
||
|
|
u64 alloc_rx_page_failed;
|
||
|
|
u64 alloc_rx_buff_failed;
|
||
|
|
u64 alloc_rx_page;
|
||
|
|
u64 rx_ipsec;
|
||
|
|
|
||
|
|
struct msix_entry *msix_entries;
|
||
|
|
|
||
|
|
/* OS defined structs */
|
||
|
|
struct net_device *netdev;
|
||
|
|
struct bpf_prog *xdp_prog;
|
||
|
|
struct pci_dev *pdev;
|
||
|
|
|
||
|
|
/* structs defined in ixgbe_vf.h */
|
||
|
|
struct ixgbe_hw hw;
|
||
|
|
u16 msg_enable;
|
||
|
|
/* Interrupt Throttle Rate */
|
||
|
|
u32 eitr_param;
|
||
|
|
|
||
|
|
struct ixgbevf_hw_stats stats;
|
||
|
|
|
||
|
|
unsigned long state;
|
||
|
|
u64 tx_busy;
|
||
|
|
unsigned int tx_ring_count;
|
||
|
|
unsigned int xdp_ring_count;
|
||
|
|
unsigned int rx_ring_count;
|
||
|
|
|
||
|
|
u8 __iomem *io_addr; /* Mainly for iounmap use */
|
||
|
|
u32 link_speed;
|
||
|
|
bool link_up;
|
||
|
|
|
||
|
|
struct timer_list service_timer;
|
||
|
|
struct work_struct service_task;
|
||
|
|
|
||
|
|
spinlock_t mbx_lock;
|
||
|
|
unsigned long last_reset;
|
||
|
|
|
||
|
|
u32 *rss_key;
|
||
|
|
u8 rss_indir_tbl[IXGBEVF_X550_VFRETA_SIZE];
|
||
|
|
u32 flags;
|
||
|
|
bool link_state;
|
||
|
|
|
||
|
|
#define IXGBEVF_FLAGS_LEGACY_RX BIT(1)
|
||
|
|
|
||
|
|
#ifdef CONFIG_XFRM
|
||
|
|
struct ixgbevf_ipsec *ipsec;
|
||
|
|
#endif /* CONFIG_XFRM */
|
||
|
|
};
|
||
|
|
|
||
|
|
enum ixbgevf_state_t {
|
||
|
|
__IXGBEVF_TESTING,
|
||
|
|
__IXGBEVF_RESETTING,
|
||
|
|
__IXGBEVF_DOWN,
|
||
|
|
__IXGBEVF_DISABLED,
|
||
|
|
__IXGBEVF_REMOVING,
|
||
|
|
__IXGBEVF_SERVICE_SCHED,
|
||
|
|
__IXGBEVF_SERVICE_INITED,
|
||
|
|
__IXGBEVF_RESET_REQUESTED,
|
||
|
|
__IXGBEVF_QUEUE_RESET_REQUESTED,
|
||
|
|
};
|
||
|
|
|
||
|
|
enum ixgbevf_boards {
|
||
|
|
board_82599_vf,
|
||
|
|
board_82599_vf_hv,
|
||
|
|
board_X540_vf,
|
||
|
|
board_X540_vf_hv,
|
||
|
|
board_X550_vf,
|
||
|
|
board_X550_vf_hv,
|
||
|
|
board_X550EM_x_vf,
|
||
|
|
board_X550EM_x_vf_hv,
|
||
|
|
board_x550em_a_vf,
|
||
|
|
};
|
||
|
|
|
||
|
|
enum ixgbevf_xcast_modes {
|
||
|
|
IXGBEVF_XCAST_MODE_NONE = 0,
|
||
|
|
IXGBEVF_XCAST_MODE_MULTI,
|
||
|
|
IXGBEVF_XCAST_MODE_ALLMULTI,
|
||
|
|
IXGBEVF_XCAST_MODE_PROMISC,
|
||
|
|
};
|
||
|
|
|
||
|
|
extern const struct ixgbevf_info ixgbevf_82599_vf_info;
|
||
|
|
extern const struct ixgbevf_info ixgbevf_X540_vf_info;
|
||
|
|
extern const struct ixgbevf_info ixgbevf_X550_vf_info;
|
||
|
|
extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_info;
|
||
|
|
extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops;
|
||
|
|
extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops_legacy;
|
||
|
|
extern const struct ixgbevf_info ixgbevf_x550em_a_vf_info;
|
||
|
|
|
||
|
|
extern const struct ixgbevf_info ixgbevf_82599_vf_hv_info;
|
||
|
|
extern const struct ixgbevf_info ixgbevf_X540_vf_hv_info;
|
||
|
|
extern const struct ixgbevf_info ixgbevf_X550_vf_hv_info;
|
||
|
|
extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_hv_info;
|
||
|
|
extern const struct ixgbe_mbx_operations ixgbevf_hv_mbx_ops;
|
||
|
|
|
||
|
|
/* needed by ethtool.c */
|
||
|
|
extern const char ixgbevf_driver_name[];
|
||
|
|
|
||
|
|
int ixgbevf_open(struct net_device *netdev);
|
||
|
|
int ixgbevf_close(struct net_device *netdev);
|
||
|
|
void ixgbevf_up(struct ixgbevf_adapter *adapter);
|
||
|
|
void ixgbevf_down(struct ixgbevf_adapter *adapter);
|
||
|
|
void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
|
||
|
|
void ixgbevf_reset(struct ixgbevf_adapter *adapter);
|
||
|
|
void ixgbevf_set_ethtool_ops(struct net_device *netdev);
|
||
|
|
int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *adapter,
|
||
|
|
struct ixgbevf_ring *rx_ring);
|
||
|
|
int ixgbevf_setup_tx_resources(struct ixgbevf_ring *);
|
||
|
|
void ixgbevf_free_rx_resources(struct ixgbevf_ring *);
|
||
|
|
void ixgbevf_free_tx_resources(struct ixgbevf_ring *);
|
||
|
|
void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
|
||
|
|
int ethtool_ioctl(struct ifreq *ifr);
|
||
|
|
|
||
|
|
extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector);
|
||
|
|
|
||
|
|
#ifdef CONFIG_IXGBEVF_IPSEC
|
||
|
|
void ixgbevf_init_ipsec_offload(struct ixgbevf_adapter *adapter);
|
||
|
|
void ixgbevf_stop_ipsec_offload(struct ixgbevf_adapter *adapter);
|
||
|
|
void ixgbevf_ipsec_restore(struct ixgbevf_adapter *adapter);
|
||
|
|
void ixgbevf_ipsec_rx(struct ixgbevf_ring *rx_ring,
|
||
|
|
union ixgbe_adv_rx_desc *rx_desc,
|
||
|
|
struct sk_buff *skb);
|
||
|
|
int ixgbevf_ipsec_tx(struct ixgbevf_ring *tx_ring,
|
||
|
|
struct ixgbevf_tx_buffer *first,
|
||
|
|
struct ixgbevf_ipsec_tx_data *itd);
|
||
|
|
#else
|
||
|
|
static inline void ixgbevf_init_ipsec_offload(struct ixgbevf_adapter *adapter)
|
||
|
|
{ }
|
||
|
|
static inline void ixgbevf_stop_ipsec_offload(struct ixgbevf_adapter *adapter)
|
||
|
|
{ }
|
||
|
|
static inline void ixgbevf_ipsec_restore(struct ixgbevf_adapter *adapter) { }
|
||
|
|
static inline void ixgbevf_ipsec_rx(struct ixgbevf_ring *rx_ring,
|
||
|
|
union ixgbe_adv_rx_desc *rx_desc,
|
||
|
|
struct sk_buff *skb) { }
|
||
|
|
static inline int ixgbevf_ipsec_tx(struct ixgbevf_ring *tx_ring,
|
||
|
|
struct ixgbevf_tx_buffer *first,
|
||
|
|
struct ixgbevf_ipsec_tx_data *itd)
|
||
|
|
{ return 0; }
|
||
|
|
#endif /* CONFIG_IXGBEVF_IPSEC */
|
||
|
|
|
||
|
|
void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter);
|
||
|
|
void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter);
|
||
|
|
|
||
|
|
#define ixgbevf_hw_to_netdev(hw) \
|
||
|
|
(((struct ixgbevf_adapter *)(hw)->back)->netdev)
|
||
|
|
|
||
|
|
#define hw_dbg(hw, format, arg...) \
|
||
|
|
netdev_dbg(ixgbevf_hw_to_netdev(hw), format, ## arg)
|
||
|
|
|
||
|
|
s32 ixgbevf_poll_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size);
|
||
|
|
s32 ixgbevf_write_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size);
|
||
|
|
|
||
|
|
#endif /* _IXGBEVF_H_ */
|