292 lines
8.4 KiB
C
292 lines
8.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*******************************************************************************
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This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
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developing this code.
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This contains the functions to handle the dma.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <asm/io.h>
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#include "dwmac1000.h"
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#include "dwmac_dma.h"
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static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
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{
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u32 value = readl(ioaddr + DMA_AXI_BUS_MODE);
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int i;
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pr_info("dwmac1000: Master AXI performs %s burst length\n",
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!(value & DMA_AXI_UNDEF) ? "fixed" : "any");
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if (axi->axi_lpi_en)
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value |= DMA_AXI_EN_LPI;
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if (axi->axi_xit_frm)
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value |= DMA_AXI_LPI_XIT_FRM;
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value &= ~DMA_AXI_WR_OSR_LMT;
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value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) <<
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DMA_AXI_WR_OSR_LMT_SHIFT;
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value &= ~DMA_AXI_RD_OSR_LMT;
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value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) <<
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DMA_AXI_RD_OSR_LMT_SHIFT;
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/* Depending on the UNDEF bit the Master AXI will perform any burst
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* length according to the BLEN programmed (by default all BLEN are
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* set).
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*/
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for (i = 0; i < AXI_BLEN; i++) {
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switch (axi->axi_blen[i]) {
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case 256:
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value |= DMA_AXI_BLEN256;
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break;
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case 128:
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value |= DMA_AXI_BLEN128;
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break;
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case 64:
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value |= DMA_AXI_BLEN64;
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break;
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case 32:
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value |= DMA_AXI_BLEN32;
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break;
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case 16:
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value |= DMA_AXI_BLEN16;
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break;
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case 8:
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value |= DMA_AXI_BLEN8;
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break;
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case 4:
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value |= DMA_AXI_BLEN4;
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break;
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}
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}
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writel(value, ioaddr + DMA_AXI_BUS_MODE);
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}
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static void dwmac1000_dma_init(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg, int atds)
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{
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u32 value = readl(ioaddr + DMA_BUS_MODE);
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int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
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int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
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/*
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* Set the DMA PBL (Programmable Burst Length) mode.
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*
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* Note: before stmmac core 3.50 this mode bit was 4xPBL, and
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* post 3.5 mode bit acts as 8*PBL.
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*/
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if (dma_cfg->pblx8)
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value |= DMA_BUS_MODE_MAXPBL;
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value |= DMA_BUS_MODE_USP;
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value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK);
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value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT);
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value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
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/* Set the Fixed burst mode */
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if (dma_cfg->fixed_burst)
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value |= DMA_BUS_MODE_FB;
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/* Mixed Burst has no effect when fb is set */
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if (dma_cfg->mixed_burst)
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value |= DMA_BUS_MODE_MB;
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if (atds)
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value |= DMA_BUS_MODE_ATDS;
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if (dma_cfg->aal)
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value |= DMA_BUS_MODE_AAL;
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writel(value, ioaddr + DMA_BUS_MODE);
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/* Mask interrupts by writing to CSR7 */
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writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
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}
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static void dwmac1000_dma_init_rx(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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dma_addr_t dma_rx_phy, u32 chan)
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{
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/* RX descriptor base address list must be written into DMA CSR3 */
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writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);
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}
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static void dwmac1000_dma_init_tx(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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dma_addr_t dma_tx_phy, u32 chan)
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{
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/* TX descriptor base address list must be written into DMA CSR4 */
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writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);
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}
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static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
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{
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csr6 &= ~DMA_CONTROL_RFA_MASK;
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csr6 &= ~DMA_CONTROL_RFD_MASK;
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/* Leave flow control disabled if receive fifo size is less than
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* 4K or 0. Otherwise, send XOFF when fifo is 1K less than full,
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* and send XON when 2K less than full.
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*/
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if (rxfifosz < 4096) {
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csr6 &= ~DMA_CONTROL_EFC;
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pr_debug("GMAC: disabling flow control, rxfifo too small(%d)\n",
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rxfifosz);
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} else {
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csr6 |= DMA_CONTROL_EFC;
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csr6 |= RFA_FULL_MINUS_1K;
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csr6 |= RFD_FULL_MINUS_2K;
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}
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return csr6;
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}
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static void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode,
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u32 channel, int fifosz, u8 qmode)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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if (mode == SF_DMA_MODE) {
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pr_debug("GMAC: enable RX store and forward mode\n");
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csr6 |= DMA_CONTROL_RSF;
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} else {
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pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
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csr6 &= ~DMA_CONTROL_RSF;
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csr6 &= DMA_CONTROL_TC_RX_MASK;
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if (mode <= 32)
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csr6 |= DMA_CONTROL_RTC_32;
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else if (mode <= 64)
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csr6 |= DMA_CONTROL_RTC_64;
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else if (mode <= 96)
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csr6 |= DMA_CONTROL_RTC_96;
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else
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csr6 |= DMA_CONTROL_RTC_128;
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}
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/* Configure flow control based on rx fifo size */
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csr6 = dwmac1000_configure_fc(csr6, fifosz);
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writel(csr6, ioaddr + DMA_CONTROL);
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}
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static void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode,
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u32 channel, int fifosz, u8 qmode)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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if (mode == SF_DMA_MODE) {
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pr_debug("GMAC: enable TX store and forward mode\n");
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/* Transmit COE type 2 cannot be done in cut-through mode. */
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csr6 |= DMA_CONTROL_TSF;
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/* Operating on second frame increase the performance
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* especially when transmit store-and-forward is used.
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*/
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csr6 |= DMA_CONTROL_OSF;
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} else {
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pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
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csr6 &= ~DMA_CONTROL_TSF;
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csr6 &= DMA_CONTROL_TC_TX_MASK;
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/* Set the transmit threshold */
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if (mode <= 32)
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csr6 |= DMA_CONTROL_TTC_32;
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else if (mode <= 64)
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csr6 |= DMA_CONTROL_TTC_64;
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else if (mode <= 128)
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csr6 |= DMA_CONTROL_TTC_128;
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else if (mode <= 192)
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csr6 |= DMA_CONTROL_TTC_192;
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else
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csr6 |= DMA_CONTROL_TTC_256;
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}
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writel(csr6, ioaddr + DMA_CONTROL);
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}
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static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
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{
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int i;
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for (i = 0; i < NUM_DWMAC1000_DMA_REGS; i++)
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if ((i < 12) || (i > 17))
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reg_space[DMA_BUS_MODE / 4 + i] =
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readl(ioaddr + DMA_BUS_MODE + i * 4);
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}
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static int dwmac1000_get_hw_feature(void __iomem *ioaddr,
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struct dma_features *dma_cap)
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{
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u32 hw_cap = readl(ioaddr + DMA_HW_FEATURE);
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if (!hw_cap) {
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/* 0x00000000 is the value read on old hardware that does not
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* implement this register
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*/
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return -EOPNOTSUPP;
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}
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dma_cap->mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
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dma_cap->mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
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dma_cap->half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
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dma_cap->hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
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dma_cap->multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
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dma_cap->pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
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dma_cap->sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
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dma_cap->pmt_remote_wake_up = (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
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dma_cap->pmt_magic_frame = (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
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/* MMC */
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dma_cap->rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
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/* IEEE 1588-2002 */
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dma_cap->time_stamp =
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(hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
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/* IEEE 1588-2008 */
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dma_cap->atime_stamp = (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
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/* 802.3az - Energy-Efficient Ethernet (EEE) */
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dma_cap->eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
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dma_cap->av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
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/* TX and RX csum */
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dma_cap->tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
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dma_cap->rx_coe_type1 = (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
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dma_cap->rx_coe_type2 = (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
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dma_cap->rxfifo_over_2048 = (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
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/* TX and RX number of channels */
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dma_cap->number_rx_channel = (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
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dma_cap->number_tx_channel = (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
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/* Alternate (enhanced) DESC mode */
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dma_cap->enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
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return 0;
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}
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static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt,
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u32 queue)
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{
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writel(riwt, ioaddr + DMA_RX_WATCHDOG);
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}
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const struct stmmac_dma_ops dwmac1000_dma_ops = {
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.reset = dwmac_dma_reset,
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.init = dwmac1000_dma_init,
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.init_rx_chan = dwmac1000_dma_init_rx,
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.init_tx_chan = dwmac1000_dma_init_tx,
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.axi = dwmac1000_dma_axi,
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.dump_regs = dwmac1000_dump_dma_regs,
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.dma_rx_mode = dwmac1000_dma_operation_mode_rx,
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.dma_tx_mode = dwmac1000_dma_operation_mode_tx,
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.enable_dma_transmission = dwmac_enable_dma_transmission,
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.enable_dma_irq = dwmac_enable_dma_irq,
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.disable_dma_irq = dwmac_disable_dma_irq,
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.start_tx = dwmac_dma_start_tx,
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.stop_tx = dwmac_dma_stop_tx,
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.start_rx = dwmac_dma_start_rx,
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.stop_rx = dwmac_dma_stop_rx,
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.dma_interrupt = dwmac_dma_interrupt,
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.get_hw_feature = dwmac1000_get_hw_feature,
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.rx_watchdog = dwmac1000_rx_watchdog,
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};
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