297 lines
8.0 KiB
C
297 lines
8.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (C) 2012-2014, 2018-2019, 2021 Intel Corporation
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* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
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* Copyright (C) 2016-2017 Intel Deutschland GmbH
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*/
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#include "iwl-drv.h"
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#include "runtime.h"
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#include "fw/api/commands.h"
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void iwl_free_fw_paging(struct iwl_fw_runtime *fwrt)
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{
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int i;
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if (!fwrt->fw_paging_db[0].fw_paging_block)
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return;
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for (i = 0; i < NUM_OF_FW_PAGING_BLOCKS; i++) {
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struct iwl_fw_paging *paging = &fwrt->fw_paging_db[i];
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if (!paging->fw_paging_block) {
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IWL_DEBUG_FW(fwrt,
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"Paging: block %d already freed, continue to next page\n",
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i);
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continue;
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}
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dma_unmap_page(fwrt->trans->dev, paging->fw_paging_phys,
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paging->fw_paging_size, DMA_BIDIRECTIONAL);
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__free_pages(paging->fw_paging_block,
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get_order(paging->fw_paging_size));
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paging->fw_paging_block = NULL;
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}
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memset(fwrt->fw_paging_db, 0, sizeof(fwrt->fw_paging_db));
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}
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IWL_EXPORT_SYMBOL(iwl_free_fw_paging);
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static int iwl_alloc_fw_paging_mem(struct iwl_fw_runtime *fwrt,
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const struct fw_img *image)
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{
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struct page *block;
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dma_addr_t phys = 0;
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int blk_idx, order, num_of_pages, size;
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if (fwrt->fw_paging_db[0].fw_paging_block)
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return 0;
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/* ensure BLOCK_2_EXP_SIZE is power of 2 of PAGING_BLOCK_SIZE */
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BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE);
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num_of_pages = image->paging_mem_size / FW_PAGING_SIZE;
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fwrt->num_of_paging_blk =
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DIV_ROUND_UP(num_of_pages, NUM_OF_PAGE_PER_GROUP);
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fwrt->num_of_pages_in_last_blk =
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num_of_pages -
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NUM_OF_PAGE_PER_GROUP * (fwrt->num_of_paging_blk - 1);
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IWL_DEBUG_FW(fwrt,
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"Paging: allocating mem for %d paging blocks, each block holds 8 pages, last block holds %d pages\n",
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fwrt->num_of_paging_blk,
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fwrt->num_of_pages_in_last_blk);
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/*
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* Allocate CSS and paging blocks in dram.
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*/
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for (blk_idx = 0; blk_idx < fwrt->num_of_paging_blk + 1; blk_idx++) {
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/* For CSS allocate 4KB, for others PAGING_BLOCK_SIZE (32K) */
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size = blk_idx ? PAGING_BLOCK_SIZE : FW_PAGING_SIZE;
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order = get_order(size);
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block = alloc_pages(GFP_KERNEL, order);
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if (!block) {
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/* free all the previous pages since we failed */
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iwl_free_fw_paging(fwrt);
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return -ENOMEM;
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}
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fwrt->fw_paging_db[blk_idx].fw_paging_block = block;
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fwrt->fw_paging_db[blk_idx].fw_paging_size = size;
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phys = dma_map_page(fwrt->trans->dev, block, 0,
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PAGE_SIZE << order,
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DMA_BIDIRECTIONAL);
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if (dma_mapping_error(fwrt->trans->dev, phys)) {
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/*
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* free the previous pages and the current one
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* since we failed to map_page.
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*/
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iwl_free_fw_paging(fwrt);
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return -ENOMEM;
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}
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fwrt->fw_paging_db[blk_idx].fw_paging_phys = phys;
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if (!blk_idx)
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IWL_DEBUG_FW(fwrt,
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"Paging: allocated 4K(CSS) bytes (order %d) for firmware paging.\n",
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order);
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else
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IWL_DEBUG_FW(fwrt,
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"Paging: allocated 32K bytes (order %d) for firmware paging.\n",
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order);
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}
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return 0;
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}
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static int iwl_fill_paging_mem(struct iwl_fw_runtime *fwrt,
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const struct fw_img *image)
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{
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int sec_idx, idx, ret;
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u32 offset = 0;
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/*
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* find where is the paging image start point:
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* if CPU2 exist and it's in paging format, then the image looks like:
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* CPU1 sections (2 or more)
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* CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between CPU1 to CPU2
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* CPU2 sections (not paged)
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* PAGING_SEPARATOR_SECTION delimiter - separate between CPU2
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* non paged to CPU2 paging sec
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* CPU2 paging CSS
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* CPU2 paging image (including instruction and data)
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*/
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for (sec_idx = 0; sec_idx < image->num_sec; sec_idx++) {
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if (image->sec[sec_idx].offset == PAGING_SEPARATOR_SECTION) {
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sec_idx++;
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break;
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}
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}
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/*
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* If paging is enabled there should be at least 2 more sections left
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* (one for CSS and one for Paging data)
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*/
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if (sec_idx >= image->num_sec - 1) {
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IWL_ERR(fwrt, "Paging: Missing CSS and/or paging sections\n");
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ret = -EINVAL;
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goto err;
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}
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/* copy the CSS block to the dram */
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IWL_DEBUG_FW(fwrt, "Paging: load paging CSS to FW, sec = %d\n",
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sec_idx);
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if (image->sec[sec_idx].len > fwrt->fw_paging_db[0].fw_paging_size) {
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IWL_ERR(fwrt, "CSS block is larger than paging size\n");
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ret = -EINVAL;
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goto err;
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}
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memcpy(page_address(fwrt->fw_paging_db[0].fw_paging_block),
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image->sec[sec_idx].data,
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image->sec[sec_idx].len);
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fwrt->fw_paging_db[0].fw_offs = image->sec[sec_idx].offset;
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dma_sync_single_for_device(fwrt->trans->dev,
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fwrt->fw_paging_db[0].fw_paging_phys,
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fwrt->fw_paging_db[0].fw_paging_size,
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DMA_BIDIRECTIONAL);
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IWL_DEBUG_FW(fwrt,
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"Paging: copied %d CSS bytes to first block\n",
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fwrt->fw_paging_db[0].fw_paging_size);
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sec_idx++;
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/*
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* Copy the paging blocks to the dram. The loop index starts
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* from 1 since the CSS block (index 0) was already copied to
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* dram. We use num_of_paging_blk + 1 to account for that.
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*/
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for (idx = 1; idx < fwrt->num_of_paging_blk + 1; idx++) {
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struct iwl_fw_paging *block = &fwrt->fw_paging_db[idx];
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int remaining = image->sec[sec_idx].len - offset;
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int len = block->fw_paging_size;
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/*
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* For the last block, we copy all that is remaining,
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* for all other blocks, we copy fw_paging_size at a
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* time. */
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if (idx == fwrt->num_of_paging_blk) {
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len = remaining;
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if (remaining !=
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fwrt->num_of_pages_in_last_blk * FW_PAGING_SIZE) {
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IWL_ERR(fwrt,
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"Paging: last block contains more data than expected %d\n",
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remaining);
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ret = -EINVAL;
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goto err;
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}
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} else if (block->fw_paging_size > remaining) {
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IWL_ERR(fwrt,
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"Paging: not enough data in other in block %d (%d)\n",
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idx, remaining);
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ret = -EINVAL;
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goto err;
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}
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memcpy(page_address(block->fw_paging_block),
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(const u8 *)image->sec[sec_idx].data + offset, len);
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block->fw_offs = image->sec[sec_idx].offset + offset;
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dma_sync_single_for_device(fwrt->trans->dev,
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block->fw_paging_phys,
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block->fw_paging_size,
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DMA_BIDIRECTIONAL);
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IWL_DEBUG_FW(fwrt,
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"Paging: copied %d paging bytes to block %d\n",
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len, idx);
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offset += block->fw_paging_size;
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}
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return 0;
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err:
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iwl_free_fw_paging(fwrt);
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return ret;
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}
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static int iwl_save_fw_paging(struct iwl_fw_runtime *fwrt,
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const struct fw_img *fw)
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{
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int ret;
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ret = iwl_alloc_fw_paging_mem(fwrt, fw);
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if (ret)
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return ret;
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return iwl_fill_paging_mem(fwrt, fw);
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}
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/* send paging cmd to FW in case CPU2 has paging image */
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static int iwl_send_paging_cmd(struct iwl_fw_runtime *fwrt,
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const struct fw_img *fw)
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{
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struct iwl_fw_paging_cmd paging_cmd = {
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.flags = cpu_to_le32(PAGING_CMD_IS_SECURED |
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PAGING_CMD_IS_ENABLED |
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(fwrt->num_of_pages_in_last_blk <<
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PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS)),
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.block_size = cpu_to_le32(BLOCK_2_EXP_SIZE),
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.block_num = cpu_to_le32(fwrt->num_of_paging_blk),
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};
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struct iwl_host_cmd hcmd = {
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.id = WIDE_ID(IWL_ALWAYS_LONG_GROUP, FW_PAGING_BLOCK_CMD),
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.len = { sizeof(paging_cmd), },
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.data = { &paging_cmd, },
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};
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int blk_idx;
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/* loop for for all paging blocks + CSS block */
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for (blk_idx = 0; blk_idx < fwrt->num_of_paging_blk + 1; blk_idx++) {
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dma_addr_t addr = fwrt->fw_paging_db[blk_idx].fw_paging_phys;
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__le32 phy_addr;
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addr = addr >> PAGE_2_EXP_SIZE;
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phy_addr = cpu_to_le32(addr);
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paging_cmd.device_phy_addr[blk_idx] = phy_addr;
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}
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return iwl_trans_send_cmd(fwrt->trans, &hcmd);
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}
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int iwl_init_paging(struct iwl_fw_runtime *fwrt, enum iwl_ucode_type type)
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{
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const struct fw_img *fw = &fwrt->fw->img[type];
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int ret;
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if (fwrt->trans->trans_cfg->gen2)
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return 0;
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/*
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* Configure and operate fw paging mechanism.
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* The driver configures the paging flow only once.
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* The CPU2 paging image is included in the IWL_UCODE_INIT image.
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*/
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if (!fw->paging_mem_size)
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return 0;
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ret = iwl_save_fw_paging(fwrt, fw);
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if (ret) {
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IWL_ERR(fwrt, "failed to save the FW paging image\n");
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return ret;
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}
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ret = iwl_send_paging_cmd(fwrt, fw);
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if (ret) {
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IWL_ERR(fwrt, "failed to send the paging cmd\n");
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iwl_free_fw_paging(fwrt);
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return ret;
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}
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return 0;
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}
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IWL_EXPORT_SYMBOL(iwl_init_paging);
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