395 lines
10 KiB
C
395 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (C) 2005-2014, 2018-2019, 2021 Intel Corporation
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*/
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include "iwl-drv.h"
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#include "iwl-debug.h"
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#include "iwl-eeprom-read.h"
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#include "iwl-io.h"
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#include "iwl-prph.h"
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#include "iwl-csr.h"
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/*
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* EEPROM access time values:
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*
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* Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
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* Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
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* When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
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* Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
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*/
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#define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
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/*
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* The device's EEPROM semaphore prevents conflicts between driver and uCode
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* when accessing the EEPROM; each access is a series of pulses to/from the
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* EEPROM chip, not a single event, so even reads could conflict if they
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* weren't arbitrated by the semaphore.
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*/
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#define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
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#define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
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static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
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{
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u16 count;
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int ret;
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for (count = 0; count < IWL_EEPROM_SEM_RETRY_LIMIT; count++) {
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/* Request semaphore */
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iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
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/* See if we got it */
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ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
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CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
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IWL_EEPROM_SEM_TIMEOUT);
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if (ret >= 0) {
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IWL_DEBUG_EEPROM(trans->dev,
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"Acquired semaphore after %d tries.\n",
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count+1);
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return ret;
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}
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}
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return ret;
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}
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static void iwl_eeprom_release_semaphore(struct iwl_trans *trans)
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{
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iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
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}
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static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp)
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{
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u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
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IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp);
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switch (gp) {
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case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
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if (!nvm_is_otp) {
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IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n",
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gp);
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return -ENOENT;
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}
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return 0;
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case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
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case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
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if (nvm_is_otp) {
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IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp);
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return -ENOENT;
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}
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return 0;
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case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
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default:
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IWL_ERR(trans,
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"bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n",
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nvm_is_otp ? "OTP" : "EEPROM", gp);
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return -ENOENT;
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}
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}
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/******************************************************************************
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*
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* OTP related functions
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*
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******************************************************************************/
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static void iwl_set_otp_access_absolute(struct iwl_trans *trans)
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{
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iwl_read32(trans, CSR_OTP_GP_REG);
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iwl_clear_bit(trans, CSR_OTP_GP_REG,
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CSR_OTP_GP_REG_OTP_ACCESS_MODE);
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}
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static int iwl_nvm_is_otp(struct iwl_trans *trans)
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{
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u32 otpgp;
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/* OTP only valid for CP/PP and after */
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switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) {
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case CSR_HW_REV_TYPE_NONE:
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IWL_ERR(trans, "Unknown hardware type\n");
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return -EIO;
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case CSR_HW_REV_TYPE_5300:
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case CSR_HW_REV_TYPE_5350:
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case CSR_HW_REV_TYPE_5100:
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case CSR_HW_REV_TYPE_5150:
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return 0;
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default:
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otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
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if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
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return 1;
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return 0;
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}
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}
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static int iwl_init_otp_access(struct iwl_trans *trans)
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{
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int ret;
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ret = iwl_finish_nic_init(trans);
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if (ret)
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return ret;
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iwl_set_bits_prph(trans, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_VAL_RESET_REQ);
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udelay(5);
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iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_VAL_RESET_REQ);
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/*
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* CSR auto clock gate disable bit -
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* this is only applicable for HW with OTP shadow RAM
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*/
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if (trans->trans_cfg->base_params->shadow_ram_support)
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iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
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CSR_RESET_LINK_PWR_MGMT_DISABLED);
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return 0;
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}
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static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,
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__le16 *eeprom_data)
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{
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int ret = 0;
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u32 r;
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u32 otpgp;
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iwl_write32(trans, CSR_EEPROM_REG,
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CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
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ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
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CSR_EEPROM_REG_READ_VALID_MSK,
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CSR_EEPROM_REG_READ_VALID_MSK,
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IWL_EEPROM_ACCESS_TIMEOUT);
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if (ret < 0) {
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IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);
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return ret;
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}
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r = iwl_read32(trans, CSR_EEPROM_REG);
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/* check for ECC errors: */
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otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
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if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
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/* stop in this case */
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/* set the uncorrectable OTP ECC bit for acknowledgment */
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iwl_set_bit(trans, CSR_OTP_GP_REG,
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CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
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IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n");
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return -EINVAL;
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}
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if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
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/* continue in this case */
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/* set the correctable OTP ECC bit for acknowledgment */
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iwl_set_bit(trans, CSR_OTP_GP_REG,
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CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
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IWL_ERR(trans, "Correctable OTP ECC error, continue read\n");
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}
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*eeprom_data = cpu_to_le16(r >> 16);
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return 0;
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}
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/*
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* iwl_is_otp_empty: check for empty OTP
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*/
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static bool iwl_is_otp_empty(struct iwl_trans *trans)
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{
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u16 next_link_addr = 0;
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__le16 link_value;
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bool is_empty = false;
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/* locate the beginning of OTP link list */
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if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) {
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if (!link_value) {
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IWL_ERR(trans, "OTP is empty\n");
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is_empty = true;
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}
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} else {
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IWL_ERR(trans, "Unable to read first block of OTP list.\n");
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is_empty = true;
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}
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return is_empty;
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}
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/*
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* iwl_find_otp_image: find EEPROM image in OTP
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* finding the OTP block that contains the EEPROM image.
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* the last valid block on the link list (the block _before_ the last block)
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* is the block we should read and used to configure the device.
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* If all the available OTP blocks are full, the last block will be the block
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* we should read and used to configure the device.
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* only perform this operation if shadow RAM is disabled
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*/
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static int iwl_find_otp_image(struct iwl_trans *trans,
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u16 *validblockaddr)
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{
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u16 next_link_addr = 0, valid_addr;
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__le16 link_value = 0;
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int usedblocks = 0;
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/* set addressing mode to absolute to traverse the link list */
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iwl_set_otp_access_absolute(trans);
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/* checking for empty OTP or error */
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if (iwl_is_otp_empty(trans))
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return -EINVAL;
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/*
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* start traverse link list
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* until reach the max number of OTP blocks
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* different devices have different number of OTP blocks
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*/
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do {
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/* save current valid block address
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* check for more block on the link list
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*/
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valid_addr = next_link_addr;
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next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
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IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n",
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usedblocks, next_link_addr);
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if (iwl_read_otp_word(trans, next_link_addr, &link_value))
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return -EINVAL;
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if (!link_value) {
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/*
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* reach the end of link list, return success and
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* set address point to the starting address
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* of the image
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*/
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*validblockaddr = valid_addr;
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/* skip first 2 bytes (link list pointer) */
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*validblockaddr += 2;
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return 0;
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}
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/* more in the link list, continue */
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usedblocks++;
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} while (usedblocks <= trans->trans_cfg->base_params->max_ll_items);
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/* OTP has no valid blocks */
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IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n");
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return -EINVAL;
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}
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/*
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* iwl_read_eeprom - read EEPROM contents
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*
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* Load the EEPROM contents from adapter and return it
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* and its size.
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*
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* NOTE: This routine uses the non-debug IO access functions.
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*/
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int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)
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{
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__le16 *e;
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u32 gp = iwl_read32(trans, CSR_EEPROM_GP);
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int sz;
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int ret;
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u16 addr;
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u16 validblockaddr = 0;
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u16 cache_addr = 0;
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int nvm_is_otp;
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if (!eeprom || !eeprom_size)
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return -EINVAL;
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nvm_is_otp = iwl_nvm_is_otp(trans);
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if (nvm_is_otp < 0)
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return nvm_is_otp;
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sz = trans->trans_cfg->base_params->eeprom_size;
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IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz);
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e = kmalloc(sz, GFP_KERNEL);
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if (!e)
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return -ENOMEM;
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ret = iwl_eeprom_verify_signature(trans, nvm_is_otp);
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if (ret < 0) {
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IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
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goto err_free;
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}
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/* Make sure driver (instead of uCode) is allowed to read EEPROM */
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ret = iwl_eeprom_acquire_semaphore(trans);
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if (ret < 0) {
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IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n");
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goto err_free;
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}
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if (nvm_is_otp) {
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ret = iwl_init_otp_access(trans);
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if (ret) {
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IWL_ERR(trans, "Failed to initialize OTP access.\n");
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goto err_unlock;
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}
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iwl_write32(trans, CSR_EEPROM_GP,
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iwl_read32(trans, CSR_EEPROM_GP) &
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~CSR_EEPROM_GP_IF_OWNER_MSK);
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iwl_set_bit(trans, CSR_OTP_GP_REG,
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CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
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CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
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/* traversing the linked list if no shadow ram supported */
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if (!trans->trans_cfg->base_params->shadow_ram_support) {
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ret = iwl_find_otp_image(trans, &validblockaddr);
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if (ret)
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goto err_unlock;
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}
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for (addr = validblockaddr; addr < validblockaddr + sz;
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addr += sizeof(u16)) {
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__le16 eeprom_data;
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ret = iwl_read_otp_word(trans, addr, &eeprom_data);
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if (ret)
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goto err_unlock;
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e[cache_addr / 2] = eeprom_data;
|
||
|
|
cache_addr += sizeof(u16);
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
/* eeprom is an array of 16bit values */
|
||
|
|
for (addr = 0; addr < sz; addr += sizeof(u16)) {
|
||
|
|
u32 r;
|
||
|
|
|
||
|
|
iwl_write32(trans, CSR_EEPROM_REG,
|
||
|
|
CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
|
||
|
|
|
||
|
|
ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
|
||
|
|
CSR_EEPROM_REG_READ_VALID_MSK,
|
||
|
|
CSR_EEPROM_REG_READ_VALID_MSK,
|
||
|
|
IWL_EEPROM_ACCESS_TIMEOUT);
|
||
|
|
if (ret < 0) {
|
||
|
|
IWL_ERR(trans,
|
||
|
|
"Time out reading EEPROM[%d]\n", addr);
|
||
|
|
goto err_unlock;
|
||
|
|
}
|
||
|
|
r = iwl_read32(trans, CSR_EEPROM_REG);
|
||
|
|
e[addr / 2] = cpu_to_le16(r >> 16);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n",
|
||
|
|
nvm_is_otp ? "OTP" : "EEPROM");
|
||
|
|
|
||
|
|
iwl_eeprom_release_semaphore(trans);
|
||
|
|
|
||
|
|
*eeprom_size = sz;
|
||
|
|
*eeprom = (u8 *)e;
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err_unlock:
|
||
|
|
iwl_eeprom_release_semaphore(trans);
|
||
|
|
err_free:
|
||
|
|
kfree(e);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
IWL_EXPORT_SYMBOL(iwl_read_eeprom);
|