361 lines
10 KiB
C
361 lines
10 KiB
C
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// SPDX-License-Identifier: ISC
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/*
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* Copyright (C) 2022 MediaTek Inc.
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*/
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#include "mt7996.h"
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#include "../dma.h"
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#include "mac.h"
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static int mt7996_poll_tx(struct napi_struct *napi, int budget)
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{
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struct mt7996_dev *dev;
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dev = container_of(napi, struct mt7996_dev, mt76.tx_napi);
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mt76_connac_tx_cleanup(&dev->mt76);
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if (napi_complete_done(napi, 0))
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mt7996_irq_enable(dev, MT_INT_TX_DONE_MCU);
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return 0;
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}
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static void mt7996_dma_config(struct mt7996_dev *dev)
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{
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#define Q_CONFIG(q, wfdma, int, id) do { \
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if (wfdma) \
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dev->q_wfdma_mask |= (1 << (q)); \
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dev->q_int_mask[(q)] = int; \
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dev->q_id[(q)] = id; \
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} while (0)
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#define MCUQ_CONFIG(q, wfdma, int, id) Q_CONFIG(q, (wfdma), (int), (id))
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#define RXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__RXQ(q), (wfdma), (int), (id))
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#define TXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__TXQ(q), (wfdma), (int), (id))
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/* rx queue */
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RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, MT7996_RXQ_MCU_WM);
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RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7996_RXQ_MCU_WA);
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/* band0/band1 */
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RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, MT7996_RXQ_BAND0);
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RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN, MT7996_RXQ_MCU_WA_MAIN);
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/* band2 */
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RXQ_CONFIG(MT_RXQ_BAND2, WFDMA0, MT_INT_RX_DONE_BAND2, MT7996_RXQ_BAND2);
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RXQ_CONFIG(MT_RXQ_BAND2_WA, WFDMA0, MT_INT_RX_DONE_WA_TRI, MT7996_RXQ_MCU_WA_TRI);
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/* data tx queue */
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TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0);
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TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);
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TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2);
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/* mcu tx queue */
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MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7996_TXQ_MCU_WM);
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MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA, MT7996_TXQ_MCU_WA);
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MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, MT7996_TXQ_FWDL);
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}
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static void __mt7996_dma_prefetch(struct mt7996_dev *dev, u32 ofs)
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{
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#define PREFETCH(_base, _depth) ((_base) << 16 | (_depth))
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/* prefetch SRAM wrapping boundary for tx/rx ring. */
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mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x2));
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mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x20, 0x2));
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mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x40, 0x4));
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mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0x80, 0x4));
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mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0xc0, 0x2));
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mt76_wr(dev, MT_TXQ_EXT_CTRL(2) + ofs, PREFETCH(0xe0, 0x4));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x120, 0x2));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x140, 0x2));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x160, 0x2));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2_WA) + ofs, PREFETCH(0x180, 0x2));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x1a0, 0x10));
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mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2) + ofs, PREFETCH(0x2a0, 0x10));
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mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1 + ofs, WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE);
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}
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void mt7996_dma_prefetch(struct mt7996_dev *dev)
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{
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__mt7996_dma_prefetch(dev, 0);
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if (dev->hif2)
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__mt7996_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0));
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}
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static void mt7996_dma_disable(struct mt7996_dev *dev, bool reset)
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{
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u32 hif1_ofs = 0;
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if (dev->hif2)
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hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
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if (reset) {
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mt76_clear(dev, MT_WFDMA0_RST,
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MT_WFDMA0_RST_DMASHDL_ALL_RST |
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MT_WFDMA0_RST_LOGIC_RST);
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mt76_set(dev, MT_WFDMA0_RST,
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MT_WFDMA0_RST_DMASHDL_ALL_RST |
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MT_WFDMA0_RST_LOGIC_RST);
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if (dev->hif2) {
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mt76_clear(dev, MT_WFDMA0_RST + hif1_ofs,
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MT_WFDMA0_RST_DMASHDL_ALL_RST |
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MT_WFDMA0_RST_LOGIC_RST);
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mt76_set(dev, MT_WFDMA0_RST + hif1_ofs,
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MT_WFDMA0_RST_DMASHDL_ALL_RST |
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MT_WFDMA0_RST_LOGIC_RST);
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}
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}
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/* disable */
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mt76_clear(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN |
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MT_WFDMA0_GLO_CFG_RX_DMA_EN |
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MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
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if (dev->hif2) {
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mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN |
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MT_WFDMA0_GLO_CFG_RX_DMA_EN |
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MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
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}
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}
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static int mt7996_dma_enable(struct mt7996_dev *dev)
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{
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u32 hif1_ofs = 0;
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u32 irq_mask;
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if (dev->hif2)
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hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
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/* reset dma idx */
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mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);
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if (dev->hif2)
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mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0);
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/* configure delay interrupt off */
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1, 0);
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2, 0);
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if (dev->hif2) {
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0);
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1 + hif1_ofs, 0);
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2 + hif1_ofs, 0);
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}
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/* configure perfetch settings */
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mt7996_dma_prefetch(dev);
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/* hif wait WFDMA idle */
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mt76_set(dev, MT_WFDMA0_BUSY_ENA,
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MT_WFDMA0_BUSY_ENA_TX_FIFO0 |
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MT_WFDMA0_BUSY_ENA_TX_FIFO1 |
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MT_WFDMA0_BUSY_ENA_RX_FIFO);
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if (dev->hif2)
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mt76_set(dev, MT_WFDMA0_BUSY_ENA + hif1_ofs,
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MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 |
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MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 |
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MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO);
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mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC,
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MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000);
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/* set WFDMA Tx/Rx */
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mt76_set(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN |
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MT_WFDMA0_GLO_CFG_RX_DMA_EN |
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MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
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/* GLO_CFG_EXT0 */
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mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT0,
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WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD |
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WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE);
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/* GLO_CFG_EXT1 */
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mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1,
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WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE);
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if (dev->hif2) {
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mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN |
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MT_WFDMA0_GLO_CFG_RX_DMA_EN |
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MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
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/* GLO_CFG_EXT0 */
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mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs,
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WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD |
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WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE);
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/* GLO_CFG_EXT1 */
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mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1 + hif1_ofs,
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WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE);
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mt76_set(dev, MT_WFDMA_HOST_CONFIG,
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MT_WFDMA_HOST_CONFIG_PDMA_BAND);
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}
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if (dev->hif2) {
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/* fix hardware limitation, pcie1's rx ring3 is not available
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* so, redirect pcie0 rx ring3 interrupt to pcie1
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*/
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mt76_set(dev, MT_WFDMA0_RX_INT_PCIE_SEL,
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MT_WFDMA0_RX_INT_SEL_RING3);
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/* TODO: redirect rx ring6 interrupt to pcie0 for wed function */
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}
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/* enable interrupts for TX/RX rings */
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irq_mask = MT_INT_RX_DONE_MCU |
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MT_INT_TX_DONE_MCU |
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MT_INT_MCU_CMD;
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if (!dev->mphy.band_idx)
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irq_mask |= MT_INT_BAND0_RX_DONE;
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if (dev->dbdc_support)
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irq_mask |= MT_INT_BAND1_RX_DONE;
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if (dev->tbtc_support)
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irq_mask |= MT_INT_BAND2_RX_DONE;
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mt7996_irq_enable(dev, irq_mask);
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return 0;
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}
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int mt7996_dma_init(struct mt7996_dev *dev)
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{
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u32 hif1_ofs = 0;
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int ret;
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mt7996_dma_config(dev);
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mt76_dma_attach(&dev->mt76);
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if (dev->hif2)
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hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
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mt7996_dma_disable(dev, true);
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/* init tx queue */
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ret = mt76_connac_init_tx_queues(dev->phy.mt76,
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MT_TXQ_ID(dev->mphy.band_idx),
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MT7996_TX_RING_SIZE,
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MT_TXQ_RING_BASE(0), 0);
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if (ret)
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return ret;
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/* command to WM */
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ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM,
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MT_MCUQ_ID(MT_MCUQ_WM),
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MT7996_TX_MCU_RING_SIZE,
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MT_MCUQ_RING_BASE(MT_MCUQ_WM));
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if (ret)
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return ret;
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/* command to WA */
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ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA,
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MT_MCUQ_ID(MT_MCUQ_WA),
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MT7996_TX_MCU_RING_SIZE,
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MT_MCUQ_RING_BASE(MT_MCUQ_WA));
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if (ret)
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return ret;
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/* firmware download */
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ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL,
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MT_MCUQ_ID(MT_MCUQ_FWDL),
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MT7996_TX_FWDL_RING_SIZE,
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MT_MCUQ_RING_BASE(MT_MCUQ_FWDL));
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if (ret)
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return ret;
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/* event from WM */
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
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MT_RXQ_ID(MT_RXQ_MCU),
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MT7996_RX_MCU_RING_SIZE,
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MT_RX_BUF_SIZE,
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MT_RXQ_RING_BASE(MT_RXQ_MCU));
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if (ret)
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return ret;
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/* event from WA */
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ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
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MT_RXQ_ID(MT_RXQ_MCU_WA),
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MT7996_RX_MCU_RING_SIZE,
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MT_RX_BUF_SIZE,
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MT_RXQ_RING_BASE(MT_RXQ_MCU_WA));
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
/* rx data queue for band0 and band1 */
|
||
|
|
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
|
||
|
|
MT_RXQ_ID(MT_RXQ_MAIN),
|
||
|
|
MT7996_RX_RING_SIZE,
|
||
|
|
MT_RX_BUF_SIZE,
|
||
|
|
MT_RXQ_RING_BASE(MT_RXQ_MAIN));
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
/* tx free notify event from WA for band0 */
|
||
|
|
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA],
|
||
|
|
MT_RXQ_ID(MT_RXQ_MAIN_WA),
|
||
|
|
MT7996_RX_MCU_RING_SIZE,
|
||
|
|
MT_RX_BUF_SIZE,
|
||
|
|
MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA));
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
if (dev->tbtc_support || dev->mphy.band_idx == MT_BAND2) {
|
||
|
|
/* rx data queue for band2 */
|
||
|
|
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2],
|
||
|
|
MT_RXQ_ID(MT_RXQ_BAND2),
|
||
|
|
MT7996_RX_RING_SIZE,
|
||
|
|
MT_RX_BUF_SIZE,
|
||
|
|
MT_RXQ_RING_BASE(MT_RXQ_BAND2) + hif1_ofs);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
/* tx free notify event from WA for band2
|
||
|
|
* use pcie0's rx ring3, but, redirect pcie0 rx ring3 interrupt to pcie1
|
||
|
|
*/
|
||
|
|
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2_WA],
|
||
|
|
MT_RXQ_ID(MT_RXQ_BAND2_WA),
|
||
|
|
MT7996_RX_MCU_RING_SIZE,
|
||
|
|
MT_RX_BUF_SIZE,
|
||
|
|
MT_RXQ_RING_BASE(MT_RXQ_BAND2_WA));
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = mt76_init_queues(dev, mt76_dma_rx_poll);
|
||
|
|
if (ret < 0)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
|
||
|
|
mt7996_poll_tx);
|
||
|
|
napi_enable(&dev->mt76.tx_napi);
|
||
|
|
|
||
|
|
mt7996_dma_enable(dev);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void mt7996_dma_cleanup(struct mt7996_dev *dev)
|
||
|
|
{
|
||
|
|
mt7996_dma_disable(dev, true);
|
||
|
|
|
||
|
|
mt76_dma_cleanup(&dev->mt76);
|
||
|
|
}
|