110 lines
2.8 KiB
C
110 lines
2.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* ACPI quirks for Tegra194 PCIe host controller
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*
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* Copyright (C) 2021 NVIDIA Corporation.
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*
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* Author: Vidya Sagar <vidyas@nvidia.com>
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*/
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#include <linux/pci.h>
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#include <linux/pci-acpi.h>
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#include <linux/pci-ecam.h>
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#include "pcie-designware.h"
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struct tegra194_pcie_ecam {
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void __iomem *config_base;
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void __iomem *iatu_base;
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void __iomem *dbi_base;
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};
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static int tegra194_acpi_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct tegra194_pcie_ecam *pcie_ecam;
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pcie_ecam = devm_kzalloc(dev, sizeof(*pcie_ecam), GFP_KERNEL);
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if (!pcie_ecam)
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return -ENOMEM;
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pcie_ecam->config_base = cfg->win;
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pcie_ecam->iatu_base = cfg->win + SZ_256K;
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pcie_ecam->dbi_base = cfg->win + SZ_512K;
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cfg->priv = pcie_ecam;
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return 0;
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}
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static void atu_reg_write(struct tegra194_pcie_ecam *pcie_ecam, int index,
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u32 val, u32 reg)
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{
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u32 offset = PCIE_ATU_UNROLL_BASE(PCIE_ATU_REGION_DIR_OB, index) +
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PCIE_ATU_VIEWPORT_BASE;
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writel(val, pcie_ecam->iatu_base + offset + reg);
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}
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static void program_outbound_atu(struct tegra194_pcie_ecam *pcie_ecam,
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int index, int type, u64 cpu_addr,
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u64 pci_addr, u64 size)
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{
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atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr),
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PCIE_ATU_LOWER_BASE);
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atu_reg_write(pcie_ecam, index, upper_32_bits(cpu_addr),
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PCIE_ATU_UPPER_BASE);
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atu_reg_write(pcie_ecam, index, lower_32_bits(pci_addr),
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PCIE_ATU_LOWER_TARGET);
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atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr + size - 1),
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PCIE_ATU_LIMIT);
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atu_reg_write(pcie_ecam, index, upper_32_bits(pci_addr),
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PCIE_ATU_UPPER_TARGET);
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atu_reg_write(pcie_ecam, index, type, PCIE_ATU_REGION_CTRL1);
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atu_reg_write(pcie_ecam, index, PCIE_ATU_ENABLE, PCIE_ATU_REGION_CTRL2);
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}
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static void __iomem *tegra194_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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struct pci_config_window *cfg = bus->sysdata;
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struct tegra194_pcie_ecam *pcie_ecam = cfg->priv;
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u32 busdev;
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int type;
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if (bus->number < cfg->busr.start || bus->number > cfg->busr.end)
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return NULL;
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if (bus->number == cfg->busr.start) {
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if (PCI_SLOT(devfn) == 0)
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return pcie_ecam->dbi_base + where;
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else
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return NULL;
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}
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busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
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PCIE_ATU_FUNC(PCI_FUNC(devfn));
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if (bus->parent->number == cfg->busr.start) {
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if (PCI_SLOT(devfn) == 0)
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type = PCIE_ATU_TYPE_CFG0;
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else
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return NULL;
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} else {
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type = PCIE_ATU_TYPE_CFG1;
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}
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program_outbound_atu(pcie_ecam, 0, type, cfg->res.start, busdev,
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SZ_256K);
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return pcie_ecam->config_base + where;
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}
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const struct pci_ecam_ops tegra194_pcie_ops = {
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.init = tegra194_acpi_init,
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.pci_ops = {
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.map_bus = tegra194_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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}
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};
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