445 lines
11 KiB
C
445 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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//
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// AMD SPI controller driver
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//
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// Copyright (c) 2020, Advanced Micro Devices, Inc.
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//
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// Author: Sanjay R Mehta <sanju.mehta@amd.com>
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#include <linux/acpi.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/spi/spi.h>
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#include <linux/iopoll.h>
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#define AMD_SPI_CTRL0_REG 0x00
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#define AMD_SPI_EXEC_CMD BIT(16)
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#define AMD_SPI_FIFO_CLEAR BIT(20)
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#define AMD_SPI_BUSY BIT(31)
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#define AMD_SPI_OPCODE_REG 0x45
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#define AMD_SPI_CMD_TRIGGER_REG 0x47
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#define AMD_SPI_TRIGGER_CMD BIT(7)
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#define AMD_SPI_OPCODE_MASK 0xFF
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#define AMD_SPI_ALT_CS_REG 0x1D
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#define AMD_SPI_ALT_CS_MASK 0x3
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#define AMD_SPI_FIFO_BASE 0x80
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#define AMD_SPI_TX_COUNT_REG 0x48
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#define AMD_SPI_RX_COUNT_REG 0x4B
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#define AMD_SPI_STATUS_REG 0x4C
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#define AMD_SPI_FIFO_SIZE 70
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#define AMD_SPI_MEM_SIZE 200
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#define AMD_SPI_ENA_REG 0x20
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#define AMD_SPI_ALT_SPD_SHIFT 20
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#define AMD_SPI_ALT_SPD_MASK GENMASK(23, AMD_SPI_ALT_SPD_SHIFT)
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#define AMD_SPI_SPI100_SHIFT 0
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#define AMD_SPI_SPI100_MASK GENMASK(AMD_SPI_SPI100_SHIFT, AMD_SPI_SPI100_SHIFT)
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#define AMD_SPI_SPEED_REG 0x6C
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#define AMD_SPI_SPD7_SHIFT 8
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#define AMD_SPI_SPD7_MASK GENMASK(13, AMD_SPI_SPD7_SHIFT)
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#define AMD_SPI_MAX_HZ 100000000
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#define AMD_SPI_MIN_HZ 800000
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/**
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* enum amd_spi_versions - SPI controller versions
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* @AMD_SPI_V1: AMDI0061 hardware version
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* @AMD_SPI_V2: AMDI0062 hardware version
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*/
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enum amd_spi_versions {
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AMD_SPI_V1 = 1,
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AMD_SPI_V2,
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};
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enum amd_spi_speed {
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F_66_66MHz,
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F_33_33MHz,
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F_22_22MHz,
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F_16_66MHz,
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F_100MHz,
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F_800KHz,
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SPI_SPD7 = 0x7,
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F_50MHz = 0x4,
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F_4MHz = 0x32,
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F_3_17MHz = 0x3F
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};
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/**
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* struct amd_spi_freq - Matches device speed with values to write in regs
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* @speed_hz: Device frequency
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* @enable_val: Value to be written to "enable register"
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* @spd7_val: Some frequencies requires to have a value written at SPISPEED register
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*/
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struct amd_spi_freq {
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u32 speed_hz;
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u32 enable_val;
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u32 spd7_val;
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};
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/**
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* struct amd_spi - SPI driver instance
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* @io_remap_addr: Start address of the SPI controller registers
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* @version: SPI controller hardware version
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* @speed_hz: Device frequency
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*/
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struct amd_spi {
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void __iomem *io_remap_addr;
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enum amd_spi_versions version;
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unsigned int speed_hz;
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};
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static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx)
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{
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return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx);
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}
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static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val)
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{
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iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
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}
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static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear)
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{
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u8 tmp = amd_spi_readreg8(amd_spi, idx);
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tmp = (tmp & ~clear) | set;
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amd_spi_writereg8(amd_spi, idx, tmp);
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}
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static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx)
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{
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return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx);
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}
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static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val)
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{
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iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
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}
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static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear)
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{
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u32 tmp = amd_spi_readreg32(amd_spi, idx);
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tmp = (tmp & ~clear) | set;
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amd_spi_writereg32(amd_spi, idx, tmp);
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}
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static void amd_spi_select_chip(struct amd_spi *amd_spi, u8 cs)
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{
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amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, cs, AMD_SPI_ALT_CS_MASK);
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}
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static inline void amd_spi_clear_chip(struct amd_spi *amd_spi, u8 chip_select)
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{
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amd_spi_writereg8(amd_spi, AMD_SPI_ALT_CS_REG, chip_select & ~AMD_SPI_ALT_CS_MASK);
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}
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static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi)
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{
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amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR);
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}
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static int amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode)
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{
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switch (amd_spi->version) {
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case AMD_SPI_V1:
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amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode,
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AMD_SPI_OPCODE_MASK);
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return 0;
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case AMD_SPI_V2:
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amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode);
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return 0;
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default:
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return -ENODEV;
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}
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}
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static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count)
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{
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amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
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}
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static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count)
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{
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amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
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}
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static int amd_spi_busy_wait(struct amd_spi *amd_spi)
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{
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u32 val;
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int reg;
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switch (amd_spi->version) {
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case AMD_SPI_V1:
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reg = AMD_SPI_CTRL0_REG;
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break;
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case AMD_SPI_V2:
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reg = AMD_SPI_STATUS_REG;
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break;
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default:
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return -ENODEV;
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}
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return readl_poll_timeout(amd_spi->io_remap_addr + reg, val,
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!(val & AMD_SPI_BUSY), 20, 2000000);
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}
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static int amd_spi_execute_opcode(struct amd_spi *amd_spi)
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{
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int ret;
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ret = amd_spi_busy_wait(amd_spi);
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if (ret)
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return ret;
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switch (amd_spi->version) {
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case AMD_SPI_V1:
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/* Set ExecuteOpCode bit in the CTRL0 register */
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amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD,
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AMD_SPI_EXEC_CMD);
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return 0;
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case AMD_SPI_V2:
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/* Trigger the command execution */
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amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG,
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AMD_SPI_TRIGGER_CMD, AMD_SPI_TRIGGER_CMD);
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return 0;
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default:
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return -ENODEV;
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}
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}
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static int amd_spi_master_setup(struct spi_device *spi)
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{
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struct amd_spi *amd_spi = spi_master_get_devdata(spi->master);
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amd_spi_clear_fifo_ptr(amd_spi);
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return 0;
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}
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static const struct amd_spi_freq amd_spi_freq[] = {
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{ AMD_SPI_MAX_HZ, F_100MHz, 0},
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{ 66660000, F_66_66MHz, 0},
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{ 50000000, SPI_SPD7, F_50MHz},
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{ 33330000, F_33_33MHz, 0},
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{ 22220000, F_22_22MHz, 0},
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{ 16660000, F_16_66MHz, 0},
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{ 4000000, SPI_SPD7, F_4MHz},
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{ 3170000, SPI_SPD7, F_3_17MHz},
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{ AMD_SPI_MIN_HZ, F_800KHz, 0},
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};
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static int amd_set_spi_freq(struct amd_spi *amd_spi, u32 speed_hz)
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{
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unsigned int i, spd7_val, alt_spd;
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if (speed_hz < AMD_SPI_MIN_HZ)
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(amd_spi_freq); i++)
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if (speed_hz >= amd_spi_freq[i].speed_hz)
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break;
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if (amd_spi->speed_hz == amd_spi_freq[i].speed_hz)
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return 0;
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amd_spi->speed_hz = amd_spi_freq[i].speed_hz;
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alt_spd = (amd_spi_freq[i].enable_val << AMD_SPI_ALT_SPD_SHIFT)
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& AMD_SPI_ALT_SPD_MASK;
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amd_spi_setclear_reg32(amd_spi, AMD_SPI_ENA_REG, alt_spd,
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AMD_SPI_ALT_SPD_MASK);
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if (amd_spi->speed_hz == AMD_SPI_MAX_HZ)
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amd_spi_setclear_reg32(amd_spi, AMD_SPI_ENA_REG, 1,
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AMD_SPI_SPI100_MASK);
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if (amd_spi_freq[i].spd7_val) {
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spd7_val = (amd_spi_freq[i].spd7_val << AMD_SPI_SPD7_SHIFT)
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& AMD_SPI_SPD7_MASK;
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amd_spi_setclear_reg32(amd_spi, AMD_SPI_SPEED_REG, spd7_val,
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AMD_SPI_SPD7_MASK);
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}
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return 0;
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}
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static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
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struct spi_master *master,
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struct spi_message *message)
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{
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struct spi_transfer *xfer = NULL;
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struct spi_device *spi = message->spi;
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u8 cmd_opcode = 0, fifo_pos = AMD_SPI_FIFO_BASE;
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u8 *buf = NULL;
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u32 i = 0;
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u32 tx_len = 0, rx_len = 0;
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list_for_each_entry(xfer, &message->transfers,
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transfer_list) {
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if (xfer->speed_hz)
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amd_set_spi_freq(amd_spi, xfer->speed_hz);
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else
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amd_set_spi_freq(amd_spi, spi->max_speed_hz);
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if (xfer->tx_buf) {
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buf = (u8 *)xfer->tx_buf;
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if (!tx_len) {
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cmd_opcode = *(u8 *)xfer->tx_buf;
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buf++;
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xfer->len--;
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}
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tx_len += xfer->len;
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/* Write data into the FIFO. */
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for (i = 0; i < xfer->len; i++)
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amd_spi_writereg8(amd_spi, fifo_pos + i, buf[i]);
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fifo_pos += xfer->len;
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}
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/* Store no. of bytes to be received from FIFO */
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if (xfer->rx_buf)
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rx_len += xfer->len;
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}
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if (!buf) {
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message->status = -EINVAL;
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goto fin_msg;
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}
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amd_spi_set_opcode(amd_spi, cmd_opcode);
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amd_spi_set_tx_count(amd_spi, tx_len);
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amd_spi_set_rx_count(amd_spi, rx_len);
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/* Execute command */
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message->status = amd_spi_execute_opcode(amd_spi);
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if (message->status)
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goto fin_msg;
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if (rx_len) {
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message->status = amd_spi_busy_wait(amd_spi);
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if (message->status)
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goto fin_msg;
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list_for_each_entry(xfer, &message->transfers, transfer_list)
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if (xfer->rx_buf) {
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buf = (u8 *)xfer->rx_buf;
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/* Read data from FIFO to receive buffer */
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for (i = 0; i < xfer->len; i++)
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buf[i] = amd_spi_readreg8(amd_spi, fifo_pos + i);
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fifo_pos += xfer->len;
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}
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}
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/* Update statistics */
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message->actual_length = tx_len + rx_len + 1;
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fin_msg:
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switch (amd_spi->version) {
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case AMD_SPI_V1:
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break;
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case AMD_SPI_V2:
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amd_spi_clear_chip(amd_spi, message->spi->chip_select);
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break;
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default:
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return -ENODEV;
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}
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spi_finalize_current_message(master);
|
||
|
|
|
||
|
|
return message->status;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int amd_spi_master_transfer(struct spi_master *master,
|
||
|
|
struct spi_message *msg)
|
||
|
|
{
|
||
|
|
struct amd_spi *amd_spi = spi_master_get_devdata(master);
|
||
|
|
struct spi_device *spi = msg->spi;
|
||
|
|
|
||
|
|
amd_spi_select_chip(amd_spi, spi->chip_select);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Extract spi_transfers from the spi message and
|
||
|
|
* program the controller.
|
||
|
|
*/
|
||
|
|
return amd_spi_fifo_xfer(amd_spi, master, msg);
|
||
|
|
}
|
||
|
|
|
||
|
|
static size_t amd_spi_max_transfer_size(struct spi_device *spi)
|
||
|
|
{
|
||
|
|
return AMD_SPI_FIFO_SIZE;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int amd_spi_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct device *dev = &pdev->dev;
|
||
|
|
struct spi_master *master;
|
||
|
|
struct amd_spi *amd_spi;
|
||
|
|
int err;
|
||
|
|
|
||
|
|
/* Allocate storage for spi_master and driver private data */
|
||
|
|
master = devm_spi_alloc_master(dev, sizeof(struct amd_spi));
|
||
|
|
if (!master)
|
||
|
|
return dev_err_probe(dev, -ENOMEM, "Error allocating SPI master\n");
|
||
|
|
|
||
|
|
amd_spi = spi_master_get_devdata(master);
|
||
|
|
amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0);
|
||
|
|
if (IS_ERR(amd_spi->io_remap_addr))
|
||
|
|
return dev_err_probe(dev, PTR_ERR(amd_spi->io_remap_addr),
|
||
|
|
"ioremap of SPI registers failed\n");
|
||
|
|
|
||
|
|
dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr);
|
||
|
|
|
||
|
|
amd_spi->version = (enum amd_spi_versions) device_get_match_data(dev);
|
||
|
|
|
||
|
|
/* Initialize the spi_master fields */
|
||
|
|
master->bus_num = 0;
|
||
|
|
master->num_chipselect = 4;
|
||
|
|
master->mode_bits = 0;
|
||
|
|
master->flags = SPI_MASTER_HALF_DUPLEX;
|
||
|
|
master->max_speed_hz = AMD_SPI_MAX_HZ;
|
||
|
|
master->min_speed_hz = AMD_SPI_MIN_HZ;
|
||
|
|
master->setup = amd_spi_master_setup;
|
||
|
|
master->transfer_one_message = amd_spi_master_transfer;
|
||
|
|
master->max_transfer_size = amd_spi_max_transfer_size;
|
||
|
|
master->max_message_size = amd_spi_max_transfer_size;
|
||
|
|
|
||
|
|
/* Register the controller with SPI framework */
|
||
|
|
err = devm_spi_register_master(dev, master);
|
||
|
|
if (err)
|
||
|
|
return dev_err_probe(dev, err, "error registering SPI controller\n");
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_ACPI
|
||
|
|
static const struct acpi_device_id spi_acpi_match[] = {
|
||
|
|
{ "AMDI0061", AMD_SPI_V1 },
|
||
|
|
{ "AMDI0062", AMD_SPI_V2 },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(acpi, spi_acpi_match);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static struct platform_driver amd_spi_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "amd_spi",
|
||
|
|
.acpi_match_table = ACPI_PTR(spi_acpi_match),
|
||
|
|
},
|
||
|
|
.probe = amd_spi_probe,
|
||
|
|
};
|
||
|
|
|
||
|
|
module_platform_driver(amd_spi_driver);
|
||
|
|
|
||
|
|
MODULE_LICENSE("Dual BSD/GPL");
|
||
|
|
MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>");
|
||
|
|
MODULE_DESCRIPTION("AMD SPI Master Controller Driver");
|