151 lines
5.0 KiB
C
151 lines
5.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd.
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* https://www.samsung.com
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* Copyright (c) 2017-2022 Tesla, Inc.
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* https://www.tesla.com
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*
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* The constants defined in this header are being used in dts
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* and fsd platform driver.
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*/
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#ifndef _DT_BINDINGS_CLOCK_FSD_H
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#define _DT_BINDINGS_CLOCK_FSD_H
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/* CMU */
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#define DOUT_CMU_PLL_SHARED0_DIV4 1
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#define DOUT_CMU_PERIC_SHARED1DIV36 2
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#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 3
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#define DOUT_CMU_PERIC_SHARED0DIV20 4
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#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 5
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#define DOUT_CMU_PLL_SHARED0_DIV6 6
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#define DOUT_CMU_FSYS0_SHARED1DIV4 7
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#define DOUT_CMU_FSYS0_SHARED0DIV4 8
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#define DOUT_CMU_FSYS1_SHARED0DIV8 9
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#define DOUT_CMU_FSYS1_SHARED0DIV4 10
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#define CMU_CPUCL_SWITCH_GATE 11
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#define DOUT_CMU_IMEM_TCUCLK 12
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#define DOUT_CMU_IMEM_ACLK 13
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#define DOUT_CMU_IMEM_DMACLK 14
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#define GAT_CMU_FSYS0_SHARED0DIV4 15
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#define CMU_NR_CLK 16
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/* PERIC */
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#define PERIC_SCLK_UART0 1
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#define PERIC_PCLK_UART0 2
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#define PERIC_SCLK_UART1 3
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#define PERIC_PCLK_UART1 4
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#define PERIC_DMA0_IPCLKPORT_ACLK 5
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#define PERIC_DMA1_IPCLKPORT_ACLK 6
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#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 7
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#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 8
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#define PERIC_PCLK_SPI0 9
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#define PERIC_SCLK_SPI0 10
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#define PERIC_PCLK_SPI1 11
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#define PERIC_SCLK_SPI1 12
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#define PERIC_PCLK_SPI2 13
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#define PERIC_SCLK_SPI2 14
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#define PERIC_PCLK_TDM0 15
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#define PERIC_PCLK_HSI2C0 16
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#define PERIC_PCLK_HSI2C1 17
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#define PERIC_PCLK_HSI2C2 18
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#define PERIC_PCLK_HSI2C3 19
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#define PERIC_PCLK_HSI2C4 20
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#define PERIC_PCLK_HSI2C5 21
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#define PERIC_PCLK_HSI2C6 22
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#define PERIC_PCLK_HSI2C7 23
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#define PERIC_MCAN0_IPCLKPORT_CCLK 24
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#define PERIC_MCAN0_IPCLKPORT_PCLK 25
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#define PERIC_MCAN1_IPCLKPORT_CCLK 26
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#define PERIC_MCAN1_IPCLKPORT_PCLK 27
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#define PERIC_MCAN2_IPCLKPORT_CCLK 28
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#define PERIC_MCAN2_IPCLKPORT_PCLK 29
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#define PERIC_MCAN3_IPCLKPORT_CCLK 30
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#define PERIC_MCAN3_IPCLKPORT_PCLK 31
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#define PERIC_PCLK_ADCIF 32
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#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 33
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#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 34
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#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 35
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#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 36
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#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 37
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#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 38
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#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 39
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#define PERIC_HCLK_TDM0 40
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#define PERIC_PCLK_TDM1 41
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#define PERIC_HCLK_TDM1 42
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#define PERIC_EQOS_PHYRXCLK_MUX 43
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#define PERIC_EQOS_PHYRXCLK 44
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#define PERIC_DOUT_RGMII_CLK 45
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#define PERIC_NR_CLK 46
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/* FSYS0 */
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#define UFS0_MPHY_REFCLK_IXTAL24 1
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#define UFS0_MPHY_REFCLK_IXTAL26 2
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#define UFS1_MPHY_REFCLK_IXTAL24 3
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#define UFS1_MPHY_REFCLK_IXTAL26 4
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#define UFS0_TOP0_HCLK_BUS 5
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#define UFS0_TOP0_ACLK 6
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#define UFS0_TOP0_CLK_UNIPRO 7
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#define UFS0_TOP0_FMP_CLK 8
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#define UFS1_TOP1_HCLK_BUS 9
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#define UFS1_TOP1_ACLK 10
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#define UFS1_TOP1_CLK_UNIPRO 11
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#define UFS1_TOP1_FMP_CLK 12
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#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 13
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#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 14
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#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 15
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#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 16
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#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17
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#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18
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#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19
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#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20
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#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21
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#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22
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#define FSYS0_NR_CLK 23
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/* FSYS1 */
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#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1
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#define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2
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#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3
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#define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4
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#define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5
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#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6
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#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7
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#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8
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#define FSYS1_NR_CLK 9
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/* IMEM */
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#define IMEM_DMA0_IPCLKPORT_ACLK 1
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#define IMEM_DMA1_IPCLKPORT_ACLK 2
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#define IMEM_WDT0_IPCLKPORT_PCLK 3
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#define IMEM_WDT1_IPCLKPORT_PCLK 4
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#define IMEM_WDT2_IPCLKPORT_PCLK 5
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#define IMEM_MCT_PCLK 6
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#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7
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#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8
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#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9
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#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10
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#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11
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#define IMEM_NR_CLK 12
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/* MFC */
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#define MFC_MFC_IPCLKPORT_ACLK 1
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#define MFC_NR_CLK 2
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/* CAM_CSI */
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#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1
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#define CAM_CSI0_1_IPCLKPORT_I_ACLK 2
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#define CAM_CSI0_2_IPCLKPORT_I_ACLK 3
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#define CAM_CSI0_3_IPCLKPORT_I_ACLK 4
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#define CAM_CSI1_0_IPCLKPORT_I_ACLK 5
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#define CAM_CSI1_1_IPCLKPORT_I_ACLK 6
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#define CAM_CSI1_2_IPCLKPORT_I_ACLK 7
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#define CAM_CSI1_3_IPCLKPORT_I_ACLK 8
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#define CAM_CSI2_0_IPCLKPORT_I_ACLK 9
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#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10
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#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11
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#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12
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#define CAM_CSI_NR_CLK 13
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#endif /*_DT_BINDINGS_CLOCK_FSD_H */
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