54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
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* Copyright (c) 2020 Western Digital Corporation or its affiliates.
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*/
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#ifndef CLOCK_K210_CLK_H
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#define CLOCK_K210_CLK_H
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/*
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* Kendryte K210 SoC clock identifiers (arbitrary values).
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*/
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#define K210_CLK_CPU 0
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#define K210_CLK_SRAM0 1
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#define K210_CLK_SRAM1 2
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#define K210_CLK_AI 3
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#define K210_CLK_DMA 4
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#define K210_CLK_FFT 5
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#define K210_CLK_ROM 6
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#define K210_CLK_DVP 7
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#define K210_CLK_APB0 8
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#define K210_CLK_APB1 9
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#define K210_CLK_APB2 10
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#define K210_CLK_I2S0 11
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#define K210_CLK_I2S1 12
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#define K210_CLK_I2S2 13
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#define K210_CLK_I2S0_M 14
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#define K210_CLK_I2S1_M 15
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#define K210_CLK_I2S2_M 16
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#define K210_CLK_WDT0 17
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#define K210_CLK_WDT1 18
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#define K210_CLK_SPI0 19
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#define K210_CLK_SPI1 20
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#define K210_CLK_SPI2 21
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#define K210_CLK_I2C0 22
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#define K210_CLK_I2C1 23
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#define K210_CLK_I2C2 24
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#define K210_CLK_SPI3 25
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#define K210_CLK_TIMER0 26
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#define K210_CLK_TIMER1 27
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#define K210_CLK_TIMER2 28
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#define K210_CLK_GPIO 29
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#define K210_CLK_UART1 30
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#define K210_CLK_UART2 31
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#define K210_CLK_UART3 32
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#define K210_CLK_FPIOA 33
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#define K210_CLK_SHA 34
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#define K210_CLK_AES 35
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#define K210_CLK_OTP 36
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#define K210_CLK_RTC 37
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#define K210_NUM_CLKS 38
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#endif /* CLOCK_K210_CLK_H */
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