203 lines
6.5 KiB
C
203 lines
6.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/*
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* Copyright (C) 2021 Ahmad Fatoum, Pengutronix
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*/
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#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
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#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
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#define JH7100_CLK_CPUNDBUS_ROOT 0
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#define JH7100_CLK_DLA_ROOT 1
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#define JH7100_CLK_DSP_ROOT 2
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#define JH7100_CLK_GMACUSB_ROOT 3
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#define JH7100_CLK_PERH0_ROOT 4
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#define JH7100_CLK_PERH1_ROOT 5
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#define JH7100_CLK_VIN_ROOT 6
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#define JH7100_CLK_VOUT_ROOT 7
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#define JH7100_CLK_AUDIO_ROOT 8
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#define JH7100_CLK_CDECHIFI4_ROOT 9
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#define JH7100_CLK_CDEC_ROOT 10
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#define JH7100_CLK_VOUTBUS_ROOT 11
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#define JH7100_CLK_CPUNBUS_ROOT_DIV 12
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#define JH7100_CLK_DSP_ROOT_DIV 13
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#define JH7100_CLK_PERH0_SRC 14
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#define JH7100_CLK_PERH1_SRC 15
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#define JH7100_CLK_PLL0_TESTOUT 16
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#define JH7100_CLK_PLL1_TESTOUT 17
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#define JH7100_CLK_PLL2_TESTOUT 18
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#define JH7100_CLK_PLL2_REF 19
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#define JH7100_CLK_CPU_CORE 20
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#define JH7100_CLK_CPU_AXI 21
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#define JH7100_CLK_AHB_BUS 22
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#define JH7100_CLK_APB1_BUS 23
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#define JH7100_CLK_APB2_BUS 24
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#define JH7100_CLK_DOM3AHB_BUS 25
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#define JH7100_CLK_DOM7AHB_BUS 26
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#define JH7100_CLK_U74_CORE0 27
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#define JH7100_CLK_U74_CORE1 28
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#define JH7100_CLK_U74_AXI 29
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#define JH7100_CLK_U74RTC_TOGGLE 30
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#define JH7100_CLK_SGDMA2P_AXI 31
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#define JH7100_CLK_DMA2PNOC_AXI 32
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#define JH7100_CLK_SGDMA2P_AHB 33
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#define JH7100_CLK_DLA_BUS 34
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#define JH7100_CLK_DLA_AXI 35
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#define JH7100_CLK_DLANOC_AXI 36
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#define JH7100_CLK_DLA_APB 37
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#define JH7100_CLK_VP6_CORE 38
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#define JH7100_CLK_VP6BUS_SRC 39
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#define JH7100_CLK_VP6_AXI 40
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#define JH7100_CLK_VCDECBUS_SRC 41
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#define JH7100_CLK_VDEC_BUS 42
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#define JH7100_CLK_VDEC_AXI 43
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#define JH7100_CLK_VDECBRG_MAIN 44
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#define JH7100_CLK_VDEC_BCLK 45
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#define JH7100_CLK_VDEC_CCLK 46
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#define JH7100_CLK_VDEC_APB 47
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#define JH7100_CLK_JPEG_AXI 48
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#define JH7100_CLK_JPEG_CCLK 49
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#define JH7100_CLK_JPEG_APB 50
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#define JH7100_CLK_GC300_2X 51
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#define JH7100_CLK_GC300_AHB 52
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#define JH7100_CLK_JPCGC300_AXIBUS 53
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#define JH7100_CLK_GC300_AXI 54
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#define JH7100_CLK_JPCGC300_MAIN 55
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#define JH7100_CLK_VENC_BUS 56
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#define JH7100_CLK_VENC_AXI 57
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#define JH7100_CLK_VENCBRG_MAIN 58
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#define JH7100_CLK_VENC_BCLK 59
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#define JH7100_CLK_VENC_CCLK 60
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#define JH7100_CLK_VENC_APB 61
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#define JH7100_CLK_DDRPLL_DIV2 62
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#define JH7100_CLK_DDRPLL_DIV4 63
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#define JH7100_CLK_DDRPLL_DIV8 64
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#define JH7100_CLK_DDROSC_DIV2 65
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#define JH7100_CLK_DDRC0 66
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#define JH7100_CLK_DDRC1 67
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#define JH7100_CLK_DDRPHY_APB 68
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#define JH7100_CLK_NOC_ROB 69
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#define JH7100_CLK_NOC_COG 70
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#define JH7100_CLK_NNE_AHB 71
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#define JH7100_CLK_NNEBUS_SRC1 72
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#define JH7100_CLK_NNE_BUS 73
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#define JH7100_CLK_NNE_AXI 74
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#define JH7100_CLK_NNENOC_AXI 75
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#define JH7100_CLK_DLASLV_AXI 76
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#define JH7100_CLK_DSPX2C_AXI 77
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#define JH7100_CLK_HIFI4_SRC 78
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#define JH7100_CLK_HIFI4_COREFREE 79
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#define JH7100_CLK_HIFI4_CORE 80
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#define JH7100_CLK_HIFI4_BUS 81
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#define JH7100_CLK_HIFI4_AXI 82
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#define JH7100_CLK_HIFI4NOC_AXI 83
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#define JH7100_CLK_SGDMA1P_BUS 84
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#define JH7100_CLK_SGDMA1P_AXI 85
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#define JH7100_CLK_DMA1P_AXI 86
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#define JH7100_CLK_X2C_AXI 87
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#define JH7100_CLK_USB_BUS 88
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#define JH7100_CLK_USB_AXI 89
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#define JH7100_CLK_USBNOC_AXI 90
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#define JH7100_CLK_USBPHY_ROOTDIV 91
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#define JH7100_CLK_USBPHY_125M 92
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#define JH7100_CLK_USBPHY_PLLDIV25M 93
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#define JH7100_CLK_USBPHY_25M 94
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#define JH7100_CLK_AUDIO_DIV 95
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#define JH7100_CLK_AUDIO_SRC 96
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#define JH7100_CLK_AUDIO_12288 97
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#define JH7100_CLK_VIN_SRC 98
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#define JH7100_CLK_ISP0_BUS 99
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#define JH7100_CLK_ISP0_AXI 100
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#define JH7100_CLK_ISP0NOC_AXI 101
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#define JH7100_CLK_ISPSLV_AXI 102
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#define JH7100_CLK_ISP1_BUS 103
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#define JH7100_CLK_ISP1_AXI 104
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#define JH7100_CLK_ISP1NOC_AXI 105
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#define JH7100_CLK_VIN_BUS 106
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#define JH7100_CLK_VIN_AXI 107
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#define JH7100_CLK_VINNOC_AXI 108
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#define JH7100_CLK_VOUT_SRC 109
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#define JH7100_CLK_DISPBUS_SRC 110
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#define JH7100_CLK_DISP_BUS 111
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#define JH7100_CLK_DISP_AXI 112
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#define JH7100_CLK_DISPNOC_AXI 113
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#define JH7100_CLK_SDIO0_AHB 114
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#define JH7100_CLK_SDIO0_CCLKINT 115
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#define JH7100_CLK_SDIO0_CCLKINT_INV 116
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#define JH7100_CLK_SDIO1_AHB 117
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#define JH7100_CLK_SDIO1_CCLKINT 118
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#define JH7100_CLK_SDIO1_CCLKINT_INV 119
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#define JH7100_CLK_GMAC_AHB 120
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#define JH7100_CLK_GMAC_ROOT_DIV 121
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#define JH7100_CLK_GMAC_PTP_REF 122
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#define JH7100_CLK_GMAC_GTX 123
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#define JH7100_CLK_GMAC_RMII_TX 124
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#define JH7100_CLK_GMAC_RMII_RX 125
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#define JH7100_CLK_GMAC_TX 126
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#define JH7100_CLK_GMAC_TX_INV 127
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#define JH7100_CLK_GMAC_RX_PRE 128
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#define JH7100_CLK_GMAC_RX_INV 129
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#define JH7100_CLK_GMAC_RMII 130
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#define JH7100_CLK_GMAC_TOPHYREF 131
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#define JH7100_CLK_SPI2AHB_AHB 132
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#define JH7100_CLK_SPI2AHB_CORE 133
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#define JH7100_CLK_EZMASTER_AHB 134
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#define JH7100_CLK_E24_AHB 135
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#define JH7100_CLK_E24RTC_TOGGLE 136
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#define JH7100_CLK_QSPI_AHB 137
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#define JH7100_CLK_QSPI_APB 138
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#define JH7100_CLK_QSPI_REF 139
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#define JH7100_CLK_SEC_AHB 140
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#define JH7100_CLK_AES 141
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#define JH7100_CLK_SHA 142
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#define JH7100_CLK_PKA 143
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#define JH7100_CLK_TRNG_APB 144
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#define JH7100_CLK_OTP_APB 145
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#define JH7100_CLK_UART0_APB 146
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#define JH7100_CLK_UART0_CORE 147
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#define JH7100_CLK_UART1_APB 148
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#define JH7100_CLK_UART1_CORE 149
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#define JH7100_CLK_SPI0_APB 150
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#define JH7100_CLK_SPI0_CORE 151
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#define JH7100_CLK_SPI1_APB 152
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#define JH7100_CLK_SPI1_CORE 153
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#define JH7100_CLK_I2C0_APB 154
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#define JH7100_CLK_I2C0_CORE 155
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#define JH7100_CLK_I2C1_APB 156
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#define JH7100_CLK_I2C1_CORE 157
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#define JH7100_CLK_GPIO_APB 158
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#define JH7100_CLK_UART2_APB 159
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#define JH7100_CLK_UART2_CORE 160
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#define JH7100_CLK_UART3_APB 161
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#define JH7100_CLK_UART3_CORE 162
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#define JH7100_CLK_SPI2_APB 163
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#define JH7100_CLK_SPI2_CORE 164
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#define JH7100_CLK_SPI3_APB 165
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#define JH7100_CLK_SPI3_CORE 166
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#define JH7100_CLK_I2C2_APB 167
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#define JH7100_CLK_I2C2_CORE 168
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#define JH7100_CLK_I2C3_APB 169
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#define JH7100_CLK_I2C3_CORE 170
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#define JH7100_CLK_WDTIMER_APB 171
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#define JH7100_CLK_WDT_CORE 172
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#define JH7100_CLK_TIMER0_CORE 173
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#define JH7100_CLK_TIMER1_CORE 174
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#define JH7100_CLK_TIMER2_CORE 175
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#define JH7100_CLK_TIMER3_CORE 176
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#define JH7100_CLK_TIMER4_CORE 177
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#define JH7100_CLK_TIMER5_CORE 178
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#define JH7100_CLK_TIMER6_CORE 179
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#define JH7100_CLK_VP6INTC_APB 180
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#define JH7100_CLK_PWM_APB 181
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#define JH7100_CLK_MSI_APB 182
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#define JH7100_CLK_TEMP_APB 183
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#define JH7100_CLK_TEMP_SENSE 184
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#define JH7100_CLK_SYSERR_APB 185
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#define JH7100_CLK_PLL0_OUT 186
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#define JH7100_CLK_PLL1_OUT 187
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#define JH7100_CLK_PLL2_OUT 188
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#define JH7100_CLK_END 189
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#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ */
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