159 lines
3.9 KiB
C
159 lines
3.9 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
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/*
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* Copyright (C) 2020 huangzhenwei@allwinnertech.com
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* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
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*/
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#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
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#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
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#define CLK_PLL_CPUX 0
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#define CLK_PLL_DDR0 1
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#define CLK_PLL_PERIPH0_4X 2
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#define CLK_PLL_PERIPH0_2X 3
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#define CLK_PLL_PERIPH0_800M 4
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#define CLK_PLL_PERIPH0 5
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#define CLK_PLL_PERIPH0_DIV3 6
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#define CLK_PLL_VIDEO0_4X 7
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#define CLK_PLL_VIDEO0_2X 8
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#define CLK_PLL_VIDEO0 9
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#define CLK_PLL_VIDEO1_4X 10
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#define CLK_PLL_VIDEO1_2X 11
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#define CLK_PLL_VIDEO1 12
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#define CLK_PLL_VE 13
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#define CLK_PLL_AUDIO0_4X 14
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#define CLK_PLL_AUDIO0_2X 15
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#define CLK_PLL_AUDIO0 16
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#define CLK_PLL_AUDIO1 17
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#define CLK_PLL_AUDIO1_DIV2 18
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#define CLK_PLL_AUDIO1_DIV5 19
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#define CLK_CPUX 20
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#define CLK_CPUX_AXI 21
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#define CLK_CPUX_APB 22
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#define CLK_PSI_AHB 23
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#define CLK_APB0 24
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#define CLK_APB1 25
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#define CLK_MBUS 26
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#define CLK_DE 27
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#define CLK_BUS_DE 28
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#define CLK_DI 29
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#define CLK_BUS_DI 30
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#define CLK_G2D 31
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#define CLK_BUS_G2D 32
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#define CLK_CE 33
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#define CLK_BUS_CE 34
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#define CLK_VE 35
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#define CLK_BUS_VE 36
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#define CLK_BUS_DMA 37
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#define CLK_BUS_MSGBOX0 38
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#define CLK_BUS_MSGBOX1 39
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#define CLK_BUS_MSGBOX2 40
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#define CLK_BUS_SPINLOCK 41
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#define CLK_BUS_HSTIMER 42
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#define CLK_AVS 43
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#define CLK_BUS_DBG 44
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#define CLK_BUS_PWM 45
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#define CLK_BUS_IOMMU 46
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#define CLK_DRAM 47
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#define CLK_MBUS_DMA 48
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#define CLK_MBUS_VE 49
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#define CLK_MBUS_CE 50
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#define CLK_MBUS_TVIN 51
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#define CLK_MBUS_CSI 52
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#define CLK_MBUS_G2D 53
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#define CLK_MBUS_RISCV 54
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#define CLK_BUS_DRAM 55
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#define CLK_MMC0 56
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#define CLK_MMC1 57
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#define CLK_MMC2 58
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#define CLK_BUS_MMC0 59
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#define CLK_BUS_MMC1 60
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#define CLK_BUS_MMC2 61
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#define CLK_BUS_UART0 62
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#define CLK_BUS_UART1 63
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#define CLK_BUS_UART2 64
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#define CLK_BUS_UART3 65
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#define CLK_BUS_UART4 66
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#define CLK_BUS_UART5 67
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#define CLK_BUS_I2C0 68
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#define CLK_BUS_I2C1 69
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#define CLK_BUS_I2C2 70
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#define CLK_BUS_I2C3 71
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#define CLK_SPI0 72
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#define CLK_SPI1 73
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#define CLK_BUS_SPI0 74
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#define CLK_BUS_SPI1 75
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#define CLK_EMAC_25M 76
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#define CLK_BUS_EMAC 77
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#define CLK_IR_TX 78
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#define CLK_BUS_IR_TX 79
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#define CLK_BUS_GPADC 80
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#define CLK_BUS_THS 81
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#define CLK_I2S0 82
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#define CLK_I2S1 83
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#define CLK_I2S2 84
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#define CLK_I2S2_ASRC 85
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#define CLK_BUS_I2S0 86
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#define CLK_BUS_I2S1 87
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#define CLK_BUS_I2S2 88
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#define CLK_SPDIF_TX 89
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#define CLK_SPDIF_RX 90
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#define CLK_BUS_SPDIF 91
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#define CLK_DMIC 92
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#define CLK_BUS_DMIC 93
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#define CLK_AUDIO_DAC 94
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#define CLK_AUDIO_ADC 95
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#define CLK_BUS_AUDIO 96
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#define CLK_USB_OHCI0 97
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#define CLK_USB_OHCI1 98
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#define CLK_BUS_OHCI0 99
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#define CLK_BUS_OHCI1 100
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#define CLK_BUS_EHCI0 101
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#define CLK_BUS_EHCI1 102
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#define CLK_BUS_OTG 103
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#define CLK_BUS_LRADC 104
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#define CLK_BUS_DPSS_TOP 105
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#define CLK_HDMI_24M 106
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#define CLK_HDMI_CEC_32K 107
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#define CLK_HDMI_CEC 108
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#define CLK_BUS_HDMI 109
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#define CLK_MIPI_DSI 110
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#define CLK_BUS_MIPI_DSI 111
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#define CLK_TCON_LCD0 112
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#define CLK_BUS_TCON_LCD0 113
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#define CLK_TCON_TV 114
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#define CLK_BUS_TCON_TV 115
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#define CLK_TVE 116
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#define CLK_BUS_TVE_TOP 117
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#define CLK_BUS_TVE 118
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#define CLK_TVD 119
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#define CLK_BUS_TVD_TOP 120
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#define CLK_BUS_TVD 121
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#define CLK_LEDC 122
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#define CLK_BUS_LEDC 123
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#define CLK_CSI_TOP 124
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#define CLK_CSI_MCLK 125
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#define CLK_BUS_CSI 126
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#define CLK_TPADC 127
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#define CLK_BUS_TPADC 128
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#define CLK_BUS_TZMA 129
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#define CLK_DSP 130
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#define CLK_BUS_DSP_CFG 131
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#define CLK_RISCV 132
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#define CLK_RISCV_AXI 133
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#define CLK_BUS_RISCV_CFG 134
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#define CLK_FANOUT_24M 135
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#define CLK_FANOUT_12M 136
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#define CLK_FANOUT_16M 137
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#define CLK_FANOUT_25M 138
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#define CLK_FANOUT_32K 139
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#define CLK_FANOUT_27M 140
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#define CLK_FANOUT_PCLK 141
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#define CLK_FANOUT0 142
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#define CLK_FANOUT1 143
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#define CLK_FANOUT2 144
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#define CLK_BUS_CAN0 145
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#define CLK_BUS_CAN1 146
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#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */
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