315 lines
7.7 KiB
C
315 lines
7.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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// Copyright 2020 NXP
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/time.h>
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#include <linux/pm_qos.h>
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#include <sound/core.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm_params.h>
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#include <linux/dma-mapping.h>
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#include "fsl_aud2htx.h"
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#include "imx-pcm.h"
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static int fsl_aud2htx_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct fsl_aud2htx *aud2htx = snd_soc_dai_get_drvdata(dai);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL,
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AUD2HTX_CTRL_EN, AUD2HTX_CTRL_EN);
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regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL_EXT,
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AUD2HTX_CTRE_DE, AUD2HTX_CTRE_DE);
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break;
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL_EXT,
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AUD2HTX_CTRE_DE, 0);
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regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL,
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AUD2HTX_CTRL_EN, 0);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct snd_soc_dai_ops fsl_aud2htx_dai_ops = {
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.trigger = fsl_aud2htx_trigger,
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};
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static int fsl_aud2htx_dai_probe(struct snd_soc_dai *cpu_dai)
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{
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struct fsl_aud2htx *aud2htx = dev_get_drvdata(cpu_dai->dev);
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/* DMA request when number of entries < WTMK_LOW */
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regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL_EXT,
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AUD2HTX_CTRE_DT_MASK, 0);
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/* Disable interrupts*/
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regmap_update_bits(aud2htx->regmap, AUD2HTX_IRQ_MASK,
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AUD2HTX_WM_HIGH_IRQ_MASK |
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AUD2HTX_WM_LOW_IRQ_MASK |
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AUD2HTX_OVF_MASK,
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AUD2HTX_WM_HIGH_IRQ_MASK |
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AUD2HTX_WM_LOW_IRQ_MASK |
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AUD2HTX_OVF_MASK);
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/* Configure watermark */
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regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL_EXT,
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AUD2HTX_CTRE_WL_MASK,
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AUD2HTX_WTMK_LOW << AUD2HTX_CTRE_WL_SHIFT);
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regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL_EXT,
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AUD2HTX_CTRE_WH_MASK,
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AUD2HTX_WTMK_HIGH << AUD2HTX_CTRE_WH_SHIFT);
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snd_soc_dai_init_dma_data(cpu_dai, &aud2htx->dma_params_tx,
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&aud2htx->dma_params_rx);
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return 0;
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}
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static struct snd_soc_dai_driver fsl_aud2htx_dai = {
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.probe = fsl_aud2htx_dai_probe,
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.playback = {
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.stream_name = "CPU-Playback",
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.channels_min = 1,
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.channels_max = 8,
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.rates = SNDRV_PCM_RATE_32000 |
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SNDRV_PCM_RATE_44100 |
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SNDRV_PCM_RATE_48000 |
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SNDRV_PCM_RATE_88200 |
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SNDRV_PCM_RATE_96000 |
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SNDRV_PCM_RATE_176400 |
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SNDRV_PCM_RATE_192000,
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.formats = FSL_AUD2HTX_FORMATS,
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},
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.ops = &fsl_aud2htx_dai_ops,
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};
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static const struct snd_soc_component_driver fsl_aud2htx_component = {
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.name = "fsl-aud2htx",
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.legacy_dai_naming = 1,
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};
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static const struct reg_default fsl_aud2htx_reg_defaults[] = {
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{AUD2HTX_CTRL, 0x00000000},
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{AUD2HTX_CTRL_EXT, 0x00000000},
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{AUD2HTX_WR, 0x00000000},
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{AUD2HTX_STATUS, 0x00000000},
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{AUD2HTX_IRQ_NOMASK, 0x00000000},
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{AUD2HTX_IRQ_MASKED, 0x00000000},
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{AUD2HTX_IRQ_MASK, 0x00000000},
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};
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static bool fsl_aud2htx_readable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case AUD2HTX_CTRL:
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case AUD2HTX_CTRL_EXT:
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case AUD2HTX_STATUS:
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case AUD2HTX_IRQ_NOMASK:
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case AUD2HTX_IRQ_MASKED:
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case AUD2HTX_IRQ_MASK:
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return true;
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default:
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return false;
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}
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}
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static bool fsl_aud2htx_writeable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case AUD2HTX_CTRL:
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case AUD2HTX_CTRL_EXT:
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case AUD2HTX_WR:
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case AUD2HTX_IRQ_NOMASK:
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case AUD2HTX_IRQ_MASKED:
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case AUD2HTX_IRQ_MASK:
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return true;
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default:
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return false;
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}
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}
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static bool fsl_aud2htx_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case AUD2HTX_STATUS:
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case AUD2HTX_IRQ_NOMASK:
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case AUD2HTX_IRQ_MASKED:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config fsl_aud2htx_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = AUD2HTX_IRQ_MASK,
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.reg_defaults = fsl_aud2htx_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(fsl_aud2htx_reg_defaults),
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.readable_reg = fsl_aud2htx_readable_reg,
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.volatile_reg = fsl_aud2htx_volatile_reg,
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.writeable_reg = fsl_aud2htx_writeable_reg,
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.cache_type = REGCACHE_RBTREE,
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};
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static const struct of_device_id fsl_aud2htx_dt_ids[] = {
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{ .compatible = "fsl,imx8mp-aud2htx",},
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{}
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};
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MODULE_DEVICE_TABLE(of, fsl_aud2htx_dt_ids);
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static irqreturn_t fsl_aud2htx_isr(int irq, void *dev_id)
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{
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return IRQ_HANDLED;
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}
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static int fsl_aud2htx_probe(struct platform_device *pdev)
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{
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struct fsl_aud2htx *aud2htx;
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struct resource *res;
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void __iomem *regs;
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int ret, irq;
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aud2htx = devm_kzalloc(&pdev->dev, sizeof(*aud2htx), GFP_KERNEL);
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if (!aud2htx)
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return -ENOMEM;
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aud2htx->pdev = pdev;
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regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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aud2htx->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
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&fsl_aud2htx_regmap_config);
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if (IS_ERR(aud2htx->regmap)) {
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dev_err(&pdev->dev, "failed to init regmap");
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return PTR_ERR(aud2htx->regmap);
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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ret = devm_request_irq(&pdev->dev, irq, fsl_aud2htx_isr, 0,
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dev_name(&pdev->dev), aud2htx);
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if (ret) {
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dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
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return ret;
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}
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aud2htx->bus_clk = devm_clk_get(&pdev->dev, "bus");
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if (IS_ERR(aud2htx->bus_clk)) {
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dev_err(&pdev->dev, "failed to get mem clock\n");
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return PTR_ERR(aud2htx->bus_clk);
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}
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aud2htx->dma_params_tx.chan_name = "tx";
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aud2htx->dma_params_tx.maxburst = AUD2HTX_MAXBURST;
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aud2htx->dma_params_tx.addr = res->start + AUD2HTX_WR;
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platform_set_drvdata(pdev, aud2htx);
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pm_runtime_enable(&pdev->dev);
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regcache_cache_only(aud2htx->regmap, true);
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/*
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* Register platform component before registering cpu dai for there
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* is not defer probe for platform component in snd_soc_add_pcm_runtime().
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*/
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ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
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if (ret) {
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dev_err(&pdev->dev, "failed to pcm register\n");
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pm_runtime_disable(&pdev->dev);
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return ret;
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}
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ret = devm_snd_soc_register_component(&pdev->dev,
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&fsl_aud2htx_component,
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&fsl_aud2htx_dai, 1);
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if (ret) {
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dev_err(&pdev->dev, "failed to register ASoC DAI\n");
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pm_runtime_disable(&pdev->dev);
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return ret;
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}
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return ret;
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}
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static int fsl_aud2htx_remove(struct platform_device *pdev)
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{
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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static int __maybe_unused fsl_aud2htx_runtime_suspend(struct device *dev)
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{
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struct fsl_aud2htx *aud2htx = dev_get_drvdata(dev);
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regcache_cache_only(aud2htx->regmap, true);
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clk_disable_unprepare(aud2htx->bus_clk);
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return 0;
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}
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static int __maybe_unused fsl_aud2htx_runtime_resume(struct device *dev)
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{
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struct fsl_aud2htx *aud2htx = dev_get_drvdata(dev);
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int ret;
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ret = clk_prepare_enable(aud2htx->bus_clk);
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if (ret)
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return ret;
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regcache_cache_only(aud2htx->regmap, false);
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regcache_mark_dirty(aud2htx->regmap);
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regcache_sync(aud2htx->regmap);
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return 0;
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}
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static const struct dev_pm_ops fsl_aud2htx_pm_ops = {
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SET_RUNTIME_PM_OPS(fsl_aud2htx_runtime_suspend,
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fsl_aud2htx_runtime_resume,
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NULL)
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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};
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static struct platform_driver fsl_aud2htx_driver = {
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.probe = fsl_aud2htx_probe,
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.remove = fsl_aud2htx_remove,
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.driver = {
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.name = "fsl-aud2htx",
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.pm = &fsl_aud2htx_pm_ops,
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.of_match_table = fsl_aud2htx_dt_ids,
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},
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};
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module_platform_driver(fsl_aud2htx_driver);
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MODULE_AUTHOR("Shengjiu Wang <Shengjiu.Wang@nxp.com>");
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MODULE_DESCRIPTION("NXP AUD2HTX driver");
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MODULE_LICENSE("GPL v2");
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