162 lines
12 KiB
JSON
162 lines
12 KiB
JSON
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[
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{
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"BriefDescription": "ARITH.FPDIV_ACTIVE",
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"CounterMask": "1",
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"EventCode": "0xb0",
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"EventName": "ARITH.FPDIV_ACTIVE",
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"SampleAfterValue": "1000003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts all microcode FP assists.",
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"EventCode": "0xc1",
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"EventName": "ASSISTS.FP",
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"PublicDescription": "Counts all microcode Floating Point assists.",
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"SampleAfterValue": "100003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "ASSISTS.SSE_AVX_MIX",
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"EventCode": "0xc1",
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"EventName": "ASSISTS.SSE_AVX_MIX",
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"SampleAfterValue": "1000003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.PORT_0",
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.PORT_1",
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"SampleAfterValue": "2000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.PORT_5",
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"SampleAfterValue": "2000003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
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"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
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"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
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"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
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"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
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"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x40"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
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"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x80"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
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"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
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"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
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"EventCode": "0xcf",
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"EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
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"SampleAfterValue": "100003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
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"EventCode": "0xcf",
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"EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
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"SampleAfterValue": "100003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
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"EventCode": "0xcf",
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"EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
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"EventCode": "0xcf",
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"EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
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"SampleAfterValue": "100003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.",
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"EventCode": "0xcf",
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"EventName": "FP_ARITH_INST_RETIRED2.SCALAR",
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"PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR",
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"SampleAfterValue": "100003",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
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"EventCode": "0xcf",
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"EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.",
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"EventCode": "0xcf",
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"EventName": "FP_ARITH_INST_RETIRED2.VECTOR",
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"PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR",
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"SampleAfterValue": "100003",
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"UMask": "0x1c"
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}
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]
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