// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals
 *
 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
 */

&cbass_mcu_wakeup {
	sms: system-controller@44083000 {
		compatible = "ti,k2g-sci";
		ti,host-id = <12>;

		mbox-names = "rx", "tx";

		mboxes = <&secure_proxy_main 11>,
			 <&secure_proxy_main 13>;

		reg-names = "debug_messages";
		reg = <0x00 0x44083000 0x00 0x1000>;

		k3_pds: power-controller {
			compatible = "ti,sci-pm-domain";
			#power-domain-cells = <2>;
		};

		k3_clks: clock-controller {
			compatible = "ti,k2g-sci-clk";
			#clock-cells = <2>;
		};

		k3_reset: reset-controller {
			compatible = "ti,sci-reset";
			#reset-cells = <2>;
		};
	};

	chipid@43000014 {
		compatible = "ti,am654-chipid";
		reg = <0x00 0x43000014 0x00 0x4>;
	};

	mcu_ram: sram@41c00000 {
		compatible = "mmio-sram";
		reg = <0x00 0x41c00000 0x00 0x100000>;
		ranges = <0x00 0x00 0x41c00000 0x100000>;
		#address-cells = <1>;
		#size-cells = <1>;
	};

	wkup_pmx0: pinctrl@4301c000 {
		compatible = "pinctrl-single";
		/* Proxy 0 addressing */
		reg = <0x00 0x4301c000 0x00 0x178>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	wkup_gpio_intr: interrupt-controller@42200000 {
		compatible = "ti,sci-intr";
		reg = <0x00 0x42200000 0x00 0x400>;
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&sms>;
		ti,sci-dev-id = <177>;
		ti,interrupt-ranges = <16 928 16>;
	};

	mcu_conf: syscon@40f00000 {
		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
		reg = <0x00 0x40f00000 0x00 0x20000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00 0x00 0x40f00000 0x20000>;

		phy_gmii_sel: phy@4040 {
			compatible = "ti,am654-phy-gmii-sel";
			reg = <0x4040 0x4>;
			#phy-cells = <1>;
		};
	};

	wkup_uart0: serial@42300000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x42300000 0x00 0x200>;
		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 397 0>;
		clock-names = "fclk";
		power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcu_uart0: serial@40a00000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x40a00000 0x00 0x200>;
		interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 149 0>;
		clock-names = "fclk";
		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	wkup_gpio0: gpio@42110000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x42110000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&wkup_gpio_intr>;
		interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <89>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 167 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	wkup_gpio1: gpio@42100000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x42100000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&wkup_gpio_intr>;
		interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <89>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 168 0>;
		clock-names = "gpio";
		status = "disabled";
	};

	wkup_i2c0: i2c@42120000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x42120000 0x00 0x100>;
		interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 279 2>;
		clock-names = "fck";
		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcu_i2c0: i2c@40b00000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x40b00000 0x00 0x100>;
		interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 277 2>;
		clock-names = "fck";
		power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcu_i2c1: i2c@40b10000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x40b10000 0x00 0x100>;
		interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 278 2>;
		clock-names = "fck";
		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
		status = "disabled";
	};

	mcu_mcan0: can@40528000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x40528000 0x00 0x200>,
		      <0x00 0x40500000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 263 6>, <&k3_clks 263 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	mcu_mcan1: can@40568000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x40568000 0x00 0x200>,
		      <0x00 0x40540000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 264 6>, <&k3_clks 264 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
		status = "disabled";
	};

	mcu_navss: bus@28380000{
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
		ti,sci-dev-id = <323>;
		dma-coherent;
		dma-ranges;

		mcu_ringacc: ringacc@2b800000 {
			compatible = "ti,am654-navss-ringacc";
			reg = <0x00 0x2b800000 0x00 0x400000>,
			      <0x00 0x2b000000 0x00 0x400000>,
			      <0x00 0x28590000 0x00 0x100>,
			      <0x00 0x2a500000 0x00 0x40000>;
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
			ti,num-rings = <286>;
			ti,sci-rm-range-gp-rings = <0x1>;
			ti,sci = <&sms>;
			ti,sci-dev-id = <328>;
			msi-parent = <&main_udmass_inta>;
		};

		mcu_udmap: dma-controller@285c0000 {
			compatible = "ti,j721e-navss-mcu-udmap";
			reg = <0x00 0x285c0000 0x00 0x100>,
			      <0x00 0x2a800000 0x00 0x40000>,
			      <0x00 0x2aa00000 0x00 0x40000>;
			reg-names = "gcfg", "rchanrt", "tchanrt";
			msi-parent = <&main_udmass_inta>;
			#dma-cells = <1>;

			ti,sci = <&sms>;
			ti,sci-dev-id = <329>;
			ti,ringacc = <&mcu_ringacc>;
			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
						<0x0f>; /* TX_HCHAN */
			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
						<0x0b>; /* RX_HCHAN */
			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
		};
	};

	mcu_cpsw: ethernet@46000000 {
		compatible = "ti,j721e-cpsw-nuss";
		#address-cells = <2>;
		#size-cells = <2>;
		reg = <0x00 0x46000000 0x00 0x200000>;
		reg-names = "cpsw_nuss";
		ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
		dma-coherent;
		clocks = <&k3_clks 63 0>;
		clock-names = "fck";
		power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;

		dmas = <&mcu_udmap 0xf000>,
		       <&mcu_udmap 0xf001>,
		       <&mcu_udmap 0xf002>,
		       <&mcu_udmap 0xf003>,
		       <&mcu_udmap 0xf004>,
		       <&mcu_udmap 0xf005>,
		       <&mcu_udmap 0xf006>,
		       <&mcu_udmap 0xf007>,
		       <&mcu_udmap 0x7000>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";
		status = "disabled";

		ethernet-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			mcu_cpsw_port1: port@1 {
				reg = <1>;
				ti,mac-only;
				label = "port1";
				ti,syscon-efuse = <&mcu_conf 0x200>;
				phys = <&phy_gmii_sel 1>;
			};
		};

		davinci_mdio: mdio@f00 {
			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
			reg = <0x00 0xf00 0x00 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&k3_clks 63 0>;
			clock-names = "fck";
			bus_freq = <1000000>;
		};

		cpts@3d000 {
			compatible = "ti,am65-cpts";
			reg = <0x00 0x3d000 0x00 0x400>;
			clocks = <&k3_clks 63 3>;
			clock-names = "cpts";
			assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */
			assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */
			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "cpts";
			ti,cpts-ext-ts-inputs = <4>;
			ti,cpts-periodic-outputs = <2>;
		};
	};
};