132 lines
4.6 KiB
YAML
132 lines
4.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Baikal-T1 Clock Control Unit PLL
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maintainers:
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- Serge Semin <fancer.lancer@gmail.com>
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description: |
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Clocks Control Unit is the core of Baikal-T1 SoC System Controller
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responsible for the chip subsystems clocking and resetting. The CCU is
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connected with an external fixed rate oscillator, which signal is transformed
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into clocks of various frequencies and then propagated to either individual
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IP-blocks or to groups of blocks (clock domains). The transformation is done
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by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
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It's logically divided into the next components:
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1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
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in general can provide any frequency supported by the CCU PLLs).
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2) PLLs clocks generators (PLLs) - described in this binding file.
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3) AXI-bus clock dividers (AXI).
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4) System devices reference clock dividers (SYS).
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which are connected with each other as shown on the next figure:
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+---------------+
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| Baikal-T1 CCU |
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| +----+------|- MIPS P5600 cores
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| +-|PLLs|------|- DDR controller
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| | +----+ |
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+----+ | | | | |
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|XTAL|--|-+ | | +---+-|
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+----+ | | | +-|AXI|-|- AXI-bus
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| | | +---+-|
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| | | |
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| | +----+---+-|- APB-bus
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| +-------|SYS|-|- Low-speed Devices
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| +---+-|- High-speed Devices
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+---------------+
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Each CCU sub-block is represented as a separate dts-node and has an
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individual driver to be bound with.
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In order to create signals of wide range frequencies the external oscillator
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output is primarily connected to a set of CCU PLLs. There are five PLLs
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to create a clock for the MIPS P5600 cores, the embedded DDR controller,
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SATA, Ethernet and PCIe domains. The last three domains though named by the
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biggest system interfaces in fact include nearly all of the rest SoC
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peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
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with an interface wrapper (so called safe PLL' clocks switcher) to simplify
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the PLL configuration procedure. The PLLs work as depicted on the next
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diagram:
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+--------------------------+
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+-->+---+ +---+ +---+ | +---+ 0|\
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CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |
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+---+ +->+---+ +---+ /->+---+ | |--->CLKOUT
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CLKOD---------C----------------+ 1| |
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+--------C--------------------------->|/
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| | ^
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Rclk-+->+---+ | |
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CLKR--->|/NR|-+ |
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+---+ |
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BYPASS--------------------------------------+
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BWADJ--->
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where Rclk is the reference clock coming from XTAL, NR - reference clock
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divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
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output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
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the binding supports the PLL dividers configuration in accordance with a
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requested rate, while bypassing and bandwidth adjustment settings can be
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added in future if it gets to be necessary.
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The PLLs CLKOUT is then either directly connected with the corresponding
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clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
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divider to create a signal required for the clock domain.
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The CCU PLL dts-node uses the common clock bindings with no custom
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parameters. The list of exported clocks can be found in
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'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
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Baikal-T1 SoC System Controller its DT node is supposed to be a child of
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later one.
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properties:
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compatible:
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const: baikal,bt1-ccu-pll
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reg:
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maxItems: 1
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"#clock-cells":
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const: 1
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clocks:
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description: External reference clock
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maxItems: 1
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clock-names:
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const: ref_clk
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additionalProperties: false
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required:
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- compatible
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- "#clock-cells"
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- clocks
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- clock-names
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examples:
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# Clock Control Unit PLL node:
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- |
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clock-controller@1f04d000 {
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compatible = "baikal,bt1-ccu-pll";
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reg = <0x1f04d000 0x028>;
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#clock-cells = <1>;
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clocks = <&clk25m>;
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clock-names = "ref_clk";
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};
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# Required external oscillator:
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- |
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clk25m: clock-oscillator-25m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "clk25m";
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};
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...
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