300 lines
10 KiB
YAML
300 lines
10 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI OMAP2+ and K3 Mailbox devices
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maintainers:
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- Suman Anna <s-anna@ti.com>
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description: |
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The OMAP Mailbox hardware facilitates communication between different
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processors using a queued mailbox interrupt mechanism. The IP block is
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external to the various processor subsystems and is connected on an
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interconnect bus. The communication is achieved through a set of registers
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for message storage and interrupt configuration registers.
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Each mailbox IP block/cluster has a certain number of h/w fifo queues and
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output interrupt lines. An output interrupt line is routed to an interrupt
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controller within a processor subsystem, and there can be more than one line
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going to a specific processor's interrupt controller. The interrupt line
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connections are fixed for an instance and are dictated by the IP integration
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into the SoC (excluding the SoCs that have an Interrupt Crossbar or an
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Interrupt Router IP). Each interrupt line is programmable through a set of
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interrupt configuration registers, and have a rx and tx interrupt source per
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h/w fifo. Communication between different processors is achieved through the
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appropriate programming of the rx and tx interrupt sources on the appropriate
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interrupt lines.
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The number of h/w fifo queues and interrupt lines dictate the usable
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registers. All the current OMAP SoCs except for the newest DRA7xx SoC has a
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single IP instance. DRA7xx has multiple instances with different number of
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h/w fifo queues and interrupt lines between different instances. The interrupt
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lines can also be routed to different processor sub-systems on DRA7xx as they
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are routed through the Crossbar, a kind of interrupt router/multiplexer. The
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K3 AM65x, J721E and J7200 SoCs has each of these instances form a cluster and
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combine multiple clusters into a single IP block present within the Main
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NavSS. The interrupt lines from all these clusters are multiplexed and routed
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to different processor subsystems over a limited number of common interrupt
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output lines of an Interrupt Router. The AM64x SoCS also uses a single IP
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block comprising of multiple clusters, but the number of clusters are
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smaller, and the interrupt output lines are connected directly to various
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processors.
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Mailbox Controller Nodes
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=========================
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A Mailbox device node is used to represent a Mailbox IP instance/cluster
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within a SoC. The sub-mailboxes (actual communication channels) are
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represented as child nodes of this parent node.
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Mailbox Users
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==============
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A device needing to communicate with a target processor device should specify
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them using the common mailbox binding properties, "mboxes" and the optional
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"mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
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for details). Each value of the mboxes property should contain a phandle to
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the mailbox controller device node and an args specifier that will be the
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phandle to the intended sub-mailbox child node to be used for communication.
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The equivalent "mbox-names" property value can be used to give a name to the
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communication channel to be used by the client user.
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$defs:
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omap-mbox-descriptor:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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The omap-mbox-descriptor is made of up of 3 cells and represents a single
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uni-directional communication channel. A typical sub-mailbox device uses
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two such channels - one for transmitting (Tx) and one for receiving (Rx).
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items:
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- description:
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mailbox fifo id used either for transmitting on ti,mbox-tx channel or
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for receiving on ti,mbox-rx channel (fifo_id). This is the hardware
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fifo number within a mailbox cluster.
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- description:
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irq identifier index number to use from the parent's interrupts data.
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Should be 0 for most of the cases, a positive index value is seen only
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on mailboxes that have multiple interrupt lines connected to the MPU
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processor (irq_id). This is an index number in the listed interrupts
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property in the DT nodes.
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- description:
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mailbox user id for identifying the interrupt line associated with
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generating a tx/rx fifo interrupt (usr_id). This is the hardware
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user id number within a mailbox cluster.
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omap-sub-mailbox:
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type: object
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description:
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The omap-sub-mailbox is a child node within a Mailbox controller device
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node and represents the actual communication channel used to send and
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receive messages between the host processor and a remote processor. Each
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child node should have a unique node name across all the different mailbox
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device nodes.
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properties:
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ti,mbox-tx:
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$ref: "#/$defs/omap-mbox-descriptor"
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description: sub-mailbox descriptor property defining a Tx fifo.
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ti,mbox-rx:
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$ref: "#/$defs/omap-mbox-descriptor"
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description: sub-mailbox descriptor property defining a Rx fifo.
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ti,mbox-send-noirq:
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type: boolean
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description:
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Quirk flag to allow the client user of this sub-mailbox to send
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messages without triggering a Tx ready interrupt, and to control
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the Tx ticker. Should be used only on sub-mailboxes used to
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communicate with WkupM3 remote processor on AM33xx/AM43xx SoCs.
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required:
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- ti,mbox-tx
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- ti,mbox-rx
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properties:
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compatible:
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enum:
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- ti,omap2-mailbox # for OMAP2420, OMAP2430 SoCs
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- ti,omap3-mailbox # for OMAP3430, OMAP3630 SoCs
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- ti,omap4-mailbox # for OMAP44xx, OMAP54xx, AM33xx, AM43xx and DRA7xx SoCs
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- ti,am654-mailbox # for K3 AM65x, J721E and J7200 SoCs
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- ti,am64-mailbox # for K3 AM64x SoCs
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reg:
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maxItems: 1
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interrupts:
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description:
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Contains the interrupt information for the mailbox device. The format is
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dependent on which interrupt controller the Mailbox device uses. The
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number of interrupts listed will at most be the value specified in
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ti,mbox-num-users property, but is usually limited by the number of
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interrupts reaching the main processor. An interrupt-parent property
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is required on SoCs where the interrupt lines are connected through a
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Interrupt Router before reaching the main processor's GIC.
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"#mbox-cells":
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const: 1
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description:
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The specifier is a phandle to an omap-sub-mailbox device.
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ti,mbox-num-users:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Number of targets (processor devices) that the mailbox device can
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interrupt.
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ti,mbox-num-fifos:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Number of h/w fifo queues within the mailbox IP block.
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ti,hwmods:
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$ref: /schemas/types.yaml#/definitions/string
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deprecated: true
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description:
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Name of the hwmod associated with the mailbox. This should be defined
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in the mailbox node only if the node is not defined as a child node of
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a corresponding sysc interconnect node.
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This property is only needed on some legacy OMAP SoCs which have not
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yet been converted to the ti,sysc interconnect hierarachy, but is
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otherwise considered obsolete.
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patternProperties:
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"^mbox-[a-z0-9-]+$":
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$ref: "#/$defs/omap-sub-mailbox"
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required:
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- compatible
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- reg
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- interrupts
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- "#mbox-cells"
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- ti,mbox-num-users
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- ti,mbox-num-fifos
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allOf:
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- if:
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properties:
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compatible:
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enum:
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- ti,am654-mailbox
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- ti,am64-mailbox
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then:
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properties:
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ti,mbox-num-users:
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const: 4
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ti,mbox-num-fifos:
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const: 16
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interrupts:
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minItems: 1
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maxItems: 4
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- if:
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properties:
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compatible:
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enum:
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- ti,omap4-mailbox
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then:
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properties:
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ti,mbox-num-users:
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enum: [3, 4]
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ti,mbox-num-fifos:
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enum: [8, 12]
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interrupts:
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minItems: 1
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maxItems: 4
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- if:
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properties:
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compatible:
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enum:
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- ti,omap3-mailbox
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then:
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properties:
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ti,mbox-num-users:
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const: 2
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ti,mbox-num-fifos:
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const: 2
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interrupts:
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minItems: 1
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maxItems: 1
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- if:
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properties:
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compatible:
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enum:
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- ti,omap2-mailbox
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then:
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properties:
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ti,mbox-num-users:
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const: 4
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ti,mbox-num-fifos:
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const: 6
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interrupts:
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minItems: 1
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maxItems: 2
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additionalProperties: false
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examples:
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- |
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/* OMAP4 */
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mailbox: mailbox@4a0f4000 {
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compatible = "ti,omap4-mailbox";
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reg = <0x4a0f4000 0x200>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <3>;
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ti,mbox-num-fifos = <8>;
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mbox_ipu: mbox-ipu {
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ti,mbox-tx = <0 0 0>;
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ti,mbox-rx = <1 0 0>;
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};
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mbox_dsp: mbox-dsp {
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ti,mbox-tx = <3 0 0>;
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ti,mbox-rx = <2 0 0>;
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};
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};
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dsp {
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mboxes = <&mailbox &mbox_dsp>;
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};
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- |
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/* AM33xx */
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mailbox1: mailbox@480c8000 {
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compatible = "ti,omap4-mailbox";
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reg = <0x480c8000 0x200>;
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interrupts = <77>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <8>;
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mbox_wkupm3: mbox-wkup-m3 {
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ti,mbox-tx = <0 0 0>;
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ti,mbox-rx = <0 0 3>;
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ti,mbox-send-noirq;
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};
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};
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- |
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/* AM65x */
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mailbox0_cluster0: mailbox@31f80000 {
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compatible = "ti,am654-mailbox";
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reg = <0x31f80000 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&intr_main_navss>;
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interrupts = <436>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-tx = <1 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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