162 lines
5.0 KiB
YAML
162 lines
5.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek JPEG Decoder
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maintainers:
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- kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
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description:
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MediaTek JPEG Decoder is the JPEG decode hardware present in MediaTek SoCs
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properties:
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compatible:
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const: mediatek,mt8195-jpgdec
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power-domains:
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maxItems: 1
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iommus:
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maxItems: 6
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description:
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Points to the respective IOMMU block with master port as argument, see
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Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
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Ports are according to the HW.
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"#address-cells":
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const: 2
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"#size-cells":
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const: 2
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ranges: true
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# Required child node:
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patternProperties:
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"^jpgdec@[0-9a-f]+$":
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type: object
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description:
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The jpeg decoder hardware device node which should be added as subnodes to
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the main jpeg node.
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properties:
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compatible:
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const: mediatek,mt8195-jpgdec-hw
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reg:
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maxItems: 1
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iommus:
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minItems: 1
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maxItems: 32
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description:
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List of the hardware port in respective IOMMU block for current Socs.
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Refer to bindings/iommu/mediatek,iommu.yaml.
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: jpgdec
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- iommus
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- interrupts
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- clocks
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- clock-names
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- power-domains
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additionalProperties: false
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required:
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- compatible
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- power-domains
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- iommus
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- ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/memory/mt8195-memory-port.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/mt8195-clk.h>
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#include <dt-bindings/power/mt8195-power.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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jpgdec-master {
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compatible = "mediatek,mt8195-jpgdec";
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power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
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iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>,
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<&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>,
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<&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>,
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<&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
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<&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
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<&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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jpgdec@1a040000 {
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compatible = "mediatek,mt8195-jpgdec-hw";
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reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
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iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
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<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
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<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
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<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
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<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
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<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
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interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vencsys CLK_VENC_JPGDEC>;
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clock-names = "jpgdec";
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power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
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};
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jpgdec@1a050000 {
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compatible = "mediatek,mt8195-jpgdec-hw";
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reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
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iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
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<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
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<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
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<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
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<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
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<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
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interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
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clock-names = "jpgdec";
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power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
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};
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jpgdec@1b040000 {
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compatible = "mediatek,mt8195-jpgdec-hw";
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reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
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iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
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<&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
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<&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
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<&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
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<&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
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<&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
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interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
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clock-names = "jpgdec";
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power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
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};
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};
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};
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