385 lines
13 KiB
YAML
385 lines
13 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# %YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
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maintainers:
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- Brian Norris <briannorris@chromium.org>
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properties:
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compatible:
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enum:
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- rockchip,rk3399-dmc
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devfreq-events:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Node to get DDR loading. Refer to
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Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: dmc_clk
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operating-points-v2: true
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center-supply:
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description:
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DMC regulator supply.
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rockchip,pmu:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon managing the "PMU general register files".
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interrupts:
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maxItems: 1
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description:
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The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
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finishes, a DCF interrupt is triggered.
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rockchip,ddr3_speed_bin:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
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DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
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datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3
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being used.
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rockchip,pd_idle:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Configure the PD_IDLE value. Defines the power-down idle period in which
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memories are placed into power-down mode if bus is idle for PD_IDLE DFI
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clock cycles.
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See also rockchip,pd-idle-ns.
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rockchip,sr_idle:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Configure the SR_IDLE value. Defines the self-refresh idle period in
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which memories are placed into self-refresh mode if bus is idle for
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SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
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See also rockchip,sr-idle-ns.
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default: 0
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rockchip,sr_mc_gate_idle:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Defines the memory self-refresh and controller clock gating idle period.
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Memories are placed into self-refresh mode and memory controller clock
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arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
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cycles.
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See also rockchip,sr-mc-gate-idle-ns.
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rockchip,srpd_lite_idle:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Defines the self-refresh power down idle period in which memories are
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placed into self-refresh power down mode if bus is idle for
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srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
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only.
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See also rockchip,srpd-lite-idle-ns.
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rockchip,standby_idle:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Defines the standby idle period in which memories are placed into
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self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
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if bus is idle for standby_idle * DFI clock cycles.
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See also rockchip,standby-idle-ns.
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rockchip,dram_dll_dis_freq:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
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than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
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Note: if DLL was bypassed, the odt will also stop working.
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rockchip,phy_dll_dis_freq:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
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is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
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Note: PHY DLL and PHY ODT are independent.
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rockchip,auto_pd_dis_freq:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Defines the auto PD disable frequency in MHz.
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rockchip,ddr3_odt_dis_freq:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1000000 # In case anyone thought this was MHz.
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description:
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When the DRAM type is DDR3, this parameter defines the ODT disable
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frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
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the ODT on the DRAM side and controller side are both disabled.
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rockchip,ddr3_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is DDR3, this parameter defines the DRAM side drive
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strength in ohms.
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default: 40
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rockchip,ddr3_odt:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is DDR3, this parameter defines the DRAM side ODT
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strength in ohms.
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default: 120
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rockchip,phy_ddr3_ca_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is DDR3, this parameter defines the phy side CA line
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(incluing command line, address line and clock line) drive strength.
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default: 40
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rockchip,phy_ddr3_dq_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is DDR3, this parameter defines the PHY side DQ line
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(including DQS/DQ/DM line) drive strength.
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default: 40
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rockchip,phy_ddr3_odt:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is DDR3, this parameter defines the PHY side ODT
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strength.
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default: 240
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rockchip,lpddr3_odt_dis_freq:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1000000 # In case anyone thought this was MHz.
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description:
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When the DRAM type is LPDDR3, this parameter defines then ODT disable
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frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
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ODT on the DRAM side and controller side are both disabled.
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rockchip,lpddr3_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
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strength in ohms.
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default: 34
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rockchip,lpddr3_odt:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
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strength in ohms.
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default: 240
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rockchip,phy_lpddr3_ca_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
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(including command line, address line and clock line) drive strength.
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default: 40
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rockchip,phy_lpddr3_dq_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
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(including DQS/DQ/DM line) drive strength.
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default: 40
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rockchip,phy_lpddr3_odt:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When dram type is LPDDR3, this parameter define the phy side odt
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strength, default value is 240.
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rockchip,lpddr4_odt_dis_freq:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1000000 # In case anyone thought this was MHz.
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description:
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When the DRAM type is LPDDR4, this parameter defines the ODT disable
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frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
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the ODT on the DRAM side and controller side are both disabled.
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rockchip,lpddr4_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
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strength in ohms.
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default: 60
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rockchip,lpddr4_dq_odt:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
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DQS/DQ line strength in ohms.
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default: 40
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rockchip,lpddr4_ca_odt:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
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CA line strength in ohms.
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default: 40
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rockchip,phy_lpddr4_ca_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
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(including command address line) drive strength.
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default: 40
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rockchip,phy_lpddr4_ck_cs_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR4, this parameter defines the PHY side clock
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line and CS line drive strength.
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default: 80
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rockchip,phy_lpddr4_dq_drv:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
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(including DQS/DQ/DM line) drive strength.
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default: 80
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rockchip,phy_lpddr4_odt:
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
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strength.
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default: 60
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rockchip,pd-idle-ns:
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description:
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Configure the PD_IDLE value in nanoseconds. Defines the power-down idle
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period in which memories are placed into power-down mode if bus is idle
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for PD_IDLE nanoseconds.
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rockchip,sr-idle-ns:
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description:
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Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
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period in which memories are placed into self-refresh mode if bus is idle
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for SR_IDLE nanoseconds.
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default: 0
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rockchip,sr-mc-gate-idle-ns:
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description:
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Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
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Memories are placed into self-refresh mode and memory controller clock
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arg gating started if bus is idle for sr_mc_gate_idle nanoseconds.
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rockchip,srpd-lite-idle-ns:
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description:
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Defines the self-refresh power down idle period in which memories are
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placed into self-refresh power down mode if bus is idle for
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srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only.
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rockchip,standby-idle-ns:
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description:
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Defines the standby idle period in which memories are placed into
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self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
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if bus is idle for standby_idle nanoseconds.
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rockchip,pd-idle-dis-freq-hz:
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description:
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Defines the power-down idle disable frequency in Hz. When the DDR
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frequency is greater than pd-idle-dis-freq, power-down idle is disabled.
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See also rockchip,pd-idle-ns.
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rockchip,sr-idle-dis-freq-hz:
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description:
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Defines the self-refresh idle disable frequency in Hz. When the DDR
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frequency is greater than sr-idle-dis-freq, self-refresh idle is
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disabled. See also rockchip,sr-idle-ns.
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rockchip,sr-mc-gate-idle-dis-freq-hz:
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description:
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Defines the self-refresh and memory-controller clock gating disable
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frequency in Hz. When the DDR frequency is greater than
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sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See also
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rockchip,sr-mc-gate-idle-ns.
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rockchip,srpd-lite-idle-dis-freq-hz:
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description:
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Defines the self-refresh power down idle disable frequency in Hz. When
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the DDR frequency is greater than srpd-lite-idle-dis-freq, memory will
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not be placed into self-refresh power down mode when idle. See also
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rockchip,srpd-lite-idle-ns.
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rockchip,standby-idle-dis-freq-hz:
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description:
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Defines the standby idle disable frequency in Hz. When the DDR frequency
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is greater than standby-idle-dis-freq, standby idle is disabled. See also
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rockchip,standby-idle-ns.
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required:
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- compatible
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- devfreq-events
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- clocks
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- clock-names
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- operating-points-v2
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- center-supply
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rk3399-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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memory-controller {
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compatible = "rockchip,rk3399-dmc";
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devfreq-events = <&dfi>;
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rockchip,pmu = <&pmu>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_DDRC>;
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clock-names = "dmc_clk";
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operating-points-v2 = <&dmc_opp_table>;
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center-supply = <&ppvar_centerlogic>;
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rockchip,pd-idle-ns = <160>;
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rockchip,sr-idle-ns = <10240>;
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rockchip,sr-mc-gate-idle-ns = <40960>;
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rockchip,srpd-lite-idle-ns = <61440>;
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rockchip,standby-idle-ns = <81920>;
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rockchip,ddr3_odt_dis_freq = <333000000>;
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rockchip,lpddr3_odt_dis_freq = <333000000>;
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rockchip,lpddr4_odt_dis_freq = <333000000>;
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rockchip,pd-idle-dis-freq-hz = <1000000000>;
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rockchip,sr-idle-dis-freq-hz = <1000000000>;
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rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
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rockchip,srpd-lite-idle-dis-freq-hz = <0>;
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rockchip,standby-idle-dis-freq-hz = <928000000>;
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};
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