115 lines
3.1 KiB
YAML
115 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI J721e System Controller Registers R/W
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description: |
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This represents the Control Module registers (CTRL_MMR0) on the SoC.
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System controller node represents a register region containing a set
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of miscellaneous registers. The registers are not cohesive enough to
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represent as any specific type of device. The typical use-case is
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for some other node's driver, or platform-specific code, to acquire
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a reference to the syscon node (e.g. by phandle, node path, or
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search using a specific compatible value), interrogate the node (or
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associated OS driver) to determine the location of the registers,
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and access the registers directly.
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maintainers:
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- Kishon Vijay Abraham I <kishon@ti.com>
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- Roger Quadros <rogerq@kernel.org>
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properties:
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compatible:
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items:
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- enum:
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- ti,j7200-system-controller
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- ti,j721e-system-controller
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- ti,j721s2-system-controller
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- const: syscon
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- const: simple-mfd
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reg:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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patternProperties:
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# Optional children
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"^mux-controller@[0-9a-f]+$":
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type: object
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description:
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This is the SERDES lane control mux.
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"^clock-controller@[0-9a-f]+$":
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type: object
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$ref: /schemas/clock/ti,am654-ehrpwm-tbclk.yaml#
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description:
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Clock provider for TI EHRPWM nodes.
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"phy@[0-9a-f]+$":
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type: object
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$ref: /schemas/phy/ti,phy-gmii-sel.yaml#
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description:
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The phy node corresponding to the ethernet MAC.
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"^chipid@[0-9a-f]+$":
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type: object
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$ref: /schemas/hwinfo/ti,k3-socinfo.yaml#
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description:
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The node corresponding to SoC chip identification.
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- ranges
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additionalProperties: false
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examples:
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- |
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scm_conf: scm-conf@100000 {
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compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
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reg = <0x00100000 0x1c000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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serdes_ln_ctrl: mux-controller@4080 {
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compatible = "mmio-mux";
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reg = <0x00004080 0x50>;
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#mux-control-cells = <1>;
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mux-reg-masks =
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<0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
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<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
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<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
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<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
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<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
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/* SERDES4 lane0/1/2/3 select */
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};
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clock-controller@4140 {
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compatible = "ti,am654-ehrpwm-tbclk";
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reg = <0x4140 0x18>;
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#clock-cells = <1>;
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};
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chipid@14 {
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compatible = "ti,am654-chipid";
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reg = <0x14 0x4>;
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};
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};
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...
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