157 lines
4.1 KiB
YAML
157 lines
4.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
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maintainers:
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- Masahiro Yamada <yamada.masahiro@socionext.com>
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properties:
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compatible:
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items:
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- enum:
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- amd,pensando-elba-sd4hc
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- microchip,mpfs-sd4hc
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- socionext,uniphier-sd4hc
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- const: cdns,sd4hc
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reg:
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minItems: 1
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maxItems: 2
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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# PHY DLL input delays:
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# They are used to delay the data valid window, and align the window to
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# sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
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# and it is increased by 2.5ns in each step.
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cdns,phy-input-delay-sd-highspeed:
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description: Value of the delay in the input path for SD high-speed timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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cdns,phy-input-delay-legacy:
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description: Value of the delay in the input path for legacy timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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cdns,phy-input-delay-sd-uhs-sdr12:
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description: Value of the delay in the input path for SD UHS SDR12 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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cdns,phy-input-delay-sd-uhs-sdr25:
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description: Value of the delay in the input path for SD UHS SDR25 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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cdns,phy-input-delay-sd-uhs-sdr50:
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description: Value of the delay in the input path for SD UHS SDR50 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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cdns,phy-input-delay-sd-uhs-ddr50:
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description: Value of the delay in the input path for SD UHS DDR50 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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cdns,phy-input-delay-mmc-highspeed:
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description: Value of the delay in the input path for MMC high-speed timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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cdns,phy-input-delay-mmc-ddr:
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description: Value of the delay in the input path for eMMC high-speed DDR timing
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# PHY DLL clock delays:
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# Each delay property represents the fraction of the clock period.
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# The approximate delay value will be
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# (<delay property value>/128)*sdmclk_clock_period.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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cdns,phy-dll-delay-sdclk:
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description: |
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Value of the delay introduced on the sdclk output for all modes except
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HS200, HS400 and HS400_ES.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x7f
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cdns,phy-dll-delay-sdclk-hsmmc:
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description: |
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Value of the delay introduced on the sdclk output for HS200, HS400 and
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HS400_ES speed modes.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x7f
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cdns,phy-dll-delay-strobe:
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description: |
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Value of the delay introduced on the dat_strobe input used in
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HS400 / HS400_ES speed modes.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x7f
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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allOf:
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- $ref: mmc-controller.yaml
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- if:
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properties:
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compatible:
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contains:
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const: amd,pensando-elba-sd4hc
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then:
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properties:
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reg:
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items:
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- description: Host controller registers
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- description: Elba byte-lane enable register for writes
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required:
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- resets
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else:
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properties:
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reg:
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maxItems: 1
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unevaluatedProperties: false
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examples:
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- |
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emmc: mmc@5a000000 {
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compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
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reg = <0x5a000000 0x400>;
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interrupts = <0 78 4>;
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clocks = <&clk 4>;
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bus-width = <8>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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cdns,phy-dll-delay-sdclk = <0>;
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};
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