243 lines
6.3 KiB
YAML
243 lines
6.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI AM654 MMC Controller
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maintainers:
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- Ulf Hansson <ulf.hansson@linaro.org>
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allOf:
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- $ref: sdhci-common.yaml#
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properties:
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compatible:
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oneOf:
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- enum:
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- ti,am62-sdhci
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- ti,am64-sdhci-4bit
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- ti,am64-sdhci-8bit
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- ti,am654-sdhci-5.1
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- ti,j721e-sdhci-4bit
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- ti,j721e-sdhci-8bit
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- items:
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- const: ti,j7200-sdhci-8bit
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- const: ti,j721e-sdhci-8bit
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- items:
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- const: ti,j7200-sdhci-4bit
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- const: ti,j721e-sdhci-4bit
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reg:
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maxItems: 2
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interrupts:
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maxItems: 1
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power-domains:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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description: Handles to input clocks
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clock-names:
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minItems: 1
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items:
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- const: clk_ahb
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- const: clk_xin
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dma-coherent:
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type: boolean
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# PHY output tap delays:
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# Used to delay the data valid window and align it to the sampling clock.
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# Binding needs to be provided for each supported speed mode otherwise the
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# corresponding mode will be disabled.
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ti,otap-del-sel-legacy:
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description: Output tap delay for SD/MMC legacy timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0xf
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ti,otap-del-sel-mmc-hs:
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description: Output tap delay for MMC high speed timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0xf
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ti,otap-del-sel-sd-hs:
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description: Output tap delay for SD high speed timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0xf
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ti,otap-del-sel-sdr12:
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description: Output tap delay for SD UHS SDR12 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0xf
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ti,otap-del-sel-sdr25:
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description: Output tap delay for SD UHS SDR25 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0xf
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ti,otap-del-sel-sdr50:
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description: Output tap delay for SD UHS SDR50 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0xf
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ti,otap-del-sel-sdr104:
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description: Output tap delay for SD UHS SDR104 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0xf
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ti,otap-del-sel-ddr50:
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description: Output tap delay for SD UHS DDR50 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0xf
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ti,otap-del-sel-ddr52:
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description: Output tap delay for eMMC DDR52 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0xf
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ti,otap-del-sel-hs200:
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description: Output tap delay for eMMC HS200 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0xf
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ti,otap-del-sel-hs400:
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description: Output tap delay for eMMC HS400 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0xf
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# PHY input tap delays:
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# Used to delay the data valid window and align it to the sampling clock for
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# modes that don't support tuning
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ti,itap-del-sel-legacy:
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description: Input tap delay for SD/MMC legacy timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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ti,itap-del-sel-mmc-hs:
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description: Input tap delay for MMC high speed timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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ti,itap-del-sel-sd-hs:
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description: Input tap delay for SD high speed timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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ti,itap-del-sel-sdr12:
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description: Input tap delay for SD UHS SDR12 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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ti,itap-del-sel-sdr25:
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description: Input tap delay for SD UHS SDR25 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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ti,itap-del-sel-ddr50:
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description: Input tap delay for MMC DDR50 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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ti,itap-del-sel-ddr52:
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description: Input tap delay for MMC DDR52 timing
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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ti,trm-icp:
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description: DLL trim select
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0xf
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ti,driver-strength-ohm:
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description: DLL drive strength in ohms
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$ref: /schemas/types.yaml#/definitions/uint32
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enum:
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- 33
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- 40
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- 50
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- 66
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- 100
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ti,strobe-sel:
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description: strobe select delay for HS400 speed mode.
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$ref: /schemas/types.yaml#/definitions/uint32
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ti,clkbuf-sel:
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description: Clock Delay Buffer Select
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$ref: /schemas/types.yaml#/definitions/uint32
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ti,fails-without-test-cd:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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When present, indicates that the CD line is not connected
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and the controller is required to be forced into Test mode
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to set the TESTCD bit.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- ti,otap-del-sel-legacy
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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mmc0: mmc@4f80000 {
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compatible = "ti,am654-sdhci-5.1";
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reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
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power-domains = <&k3_pds 47>;
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clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
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clock-names = "clk_ahb", "clk_xin";
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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sdhci-caps-mask = <0x80000007 0x0>;
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mmc-ddr-1_8v;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-mmc-hs = <0x0>;
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ti,otap-del-sel-ddr52 = <0x5>;
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ti,otap-del-sel-hs200 = <0x5>;
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ti,otap-del-sel-hs400 = <0x0>;
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ti,itap-del-sel-legacy = <0x10>;
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ti,itap-del-sel-mmc-hs = <0xa>;
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ti,itap-del-sel-ddr52 = <0x3>;
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ti,trm-icp = <0x8>;
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};
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};
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