145 lines
3.4 KiB
YAML
145 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2022 StarFive Technology Co., Ltd.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 DWMAC glue layer
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maintainers:
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- Emil Renner Berthing <kernel@esmil.dk>
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- Samin Guo <samin.guo@starfivetech.com>
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select:
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properties:
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compatible:
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contains:
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enum:
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- starfive,jh7110-dwmac
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- starfive,jh7110-dwmac
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- const: snps,dwmac-5.20
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reg:
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maxItems: 1
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clocks:
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items:
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- description: GMAC main clock
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- description: GMAC AHB clock
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- description: PTP clock
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- description: TX clock
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- description: GTX clock
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clock-names:
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items:
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- const: stmmaceth
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- const: pclk
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- const: ptp_ref
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- const: tx
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- const: gtx
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interrupts:
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minItems: 3
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maxItems: 3
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interrupt-names:
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minItems: 3
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maxItems: 3
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resets:
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items:
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- description: MAC Reset signal.
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- description: AHB Reset signal.
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reset-names:
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items:
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- const: stmmaceth
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- const: ahb
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starfive,tx-use-rgmii-clk:
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description:
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Tx clock is provided by external rgmii clock.
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type: boolean
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starfive,syscon:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to syscon that configures phy mode
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- description: Offset of phy mode selection
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- description: Shift of phy mode selection
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description:
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A phandle to syscon with two arguments that configure phy mode.
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The argument one is the offset of phy mode selection, the
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argument two is the shift of phy mode selection.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- resets
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- reset-names
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allOf:
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- $ref: snps,dwmac.yaml#
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unevaluatedProperties: false
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examples:
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- |
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ethernet@16030000 {
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compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
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reg = <0x16030000 0x10000>;
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clocks = <&clk 3>, <&clk 2>, <&clk 109>,
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<&clk 6>, <&clk 111>;
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clock-names = "stmmaceth", "pclk", "ptp_ref",
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"tx", "gtx";
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resets = <&rst 1>, <&rst 2>;
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reset-names = "stmmaceth", "ahb";
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interrupts = <7>, <6>, <5>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
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phy-mode = "rgmii-id";
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snps,multicast-filter-bins = <64>;
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snps,perfect-filter-entries = <8>;
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rx-fifo-depth = <2048>;
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tx-fifo-depth = <2048>;
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snps,fixed-burst;
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snps,no-pbl-x8;
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snps,tso;
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snps,force_thresh_dma_mode;
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snps,axi-config = <&stmmac_axi_setup>;
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snps,en-tx-lpi-clockgating;
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snps,txpbl = <16>;
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snps,rxpbl = <16>;
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starfive,syscon = <&aon_syscon 0xc 0x12>;
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phy-handle = <&phy0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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stmmac_axi_setup: stmmac-axi-config {
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snps,lpi_en;
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snps,wr_osr_lmt = <4>;
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snps,rd_osr_lmt = <4>;
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snps,blen = <256 128 64 32 0 0 0>;
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};
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};
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