164 lines
4.4 KiB
YAML
164 lines
4.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2019 BayLibre, SAS
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32 / MCU DWMAC glue layer controller
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maintainers:
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- Alexandre Torgue <alexandre.torgue@foss.st.com>
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- Christophe Roullier <christophe.roullier@foss.st.com>
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description:
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This file documents platform glue layer for stmmac.
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# We need a select here so we don't match all nodes with 'snps,dwmac'
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select:
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properties:
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compatible:
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contains:
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enum:
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- st,stm32-dwmac
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- st,stm32mp1-dwmac
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required:
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- compatible
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allOf:
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- $ref: snps,dwmac.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- st,stm32mp1-dwmac
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- const: snps,dwmac-4.20a
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- items:
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- enum:
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- st,stm32-dwmac
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- const: snps,dwmac-4.10a
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- items:
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- enum:
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- st,stm32-dwmac
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- const: snps,dwmac-3.50a
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reg: true
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reg-names:
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items:
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- const: stmmaceth
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clocks:
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minItems: 3
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items:
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- description: GMAC main clock
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- description: MAC TX clock
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- description: MAC RX clock
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- description: For MPU family, used for power mode
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- description: For MPU family, used for PHY without quartz
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- description: PTP clock
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clock-names:
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minItems: 3
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maxItems: 6
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contains:
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enum:
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- stmmaceth
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- mac-clk-tx
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- mac-clk-rx
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- ethstp
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- eth-ck
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- ptp_ref
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st,syscon:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to the syscon node which encompases the glue register
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- description: offset of the control register
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description:
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Should be phandle/offset pair. The phandle to the syscon node which
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encompases the glue register, and the offset of the control register
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st,eth-clk-sel:
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description:
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set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
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type: boolean
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st,eth-ref-clk-sel:
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description:
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set this property in RMII mode when you have PHY without crystal 50MHz and want to
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select RCC clock instead of ETH_REF_CLK.
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type: boolean
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required:
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- compatible
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- clocks
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- clock-names
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- st,syscon
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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#include <dt-bindings/mfd/stm32h7-rcc.h>
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//Example 1
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ethernet0: ethernet@5800a000 {
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compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
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reg = <0x5800a000 0x2000>;
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reg-names = "stmmaceth";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clock-names = "stmmaceth",
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"mac-clk-tx",
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"mac-clk-rx",
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"ethstp",
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"eth-ck";
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clocks = <&rcc ETHMAC>,
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<&rcc ETHTX>,
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<&rcc ETHRX>,
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<&rcc ETHSTP>,
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<&rcc ETHCK_K>;
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st,syscon = <&syscfg 0x4>;
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snps,pbl = <2>;
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snps,axi-config = <&stmmac_axi_config_0>;
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snps,tso;
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phy-mode = "rgmii";
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};
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- |
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//Example 2 (MCU example)
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ethernet1: ethernet@40028000 {
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compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
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reg = <0x40028000 0x8000>;
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reg-names = "stmmaceth";
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interrupts = <0 61 0>, <0 62 0>;
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interrupt-names = "macirq", "eth_wake_irq";
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clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
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clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
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st,syscon = <&syscfg 0x4>;
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snps,pbl = <8>;
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snps,mixed-burst;
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phy-mode = "mii";
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};
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- |
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//Example 3
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ethernet2: ethernet@40027000 {
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compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
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reg = <0x40028000 0x8000>;
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reg-names = "stmmaceth";
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interrupts = <61>;
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interrupt-names = "macirq";
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clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
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clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
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st,syscon = <&syscfg 0x4>;
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snps,pbl = <8>;
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phy-mode = "mii";
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};
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