146 lines
3.2 KiB
YAML
146 lines
3.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: DesignWare based PCIe controller on Rockchip SoCs
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maintainers:
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- Shawn Lin <shawn.lin@rock-chips.com>
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- Simon Xue <xxm@rock-chips.com>
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- Heiko Stuebner <heiko@sntech.de>
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description: |+
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RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
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PCIe IP and thus inherits all the common properties defined in
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snps,dw-pcie.yaml.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:
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oneOf:
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- const: rockchip,rk3568-pcie
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- items:
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- enum:
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- rockchip,rk3588-pcie
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- const: rockchip,rk3568-pcie
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reg:
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items:
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- description: Data Bus Interface (DBI) registers
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- description: Rockchip designed configuration registers
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- description: Config registers
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reg-names:
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items:
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- const: dbi
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- const: apb
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- const: config
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clocks:
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minItems: 5
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items:
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- description: AHB clock for PCIe master
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- description: AHB clock for PCIe slave
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- description: AHB clock for PCIe dbi
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- description: APB clock for PCIe
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- description: Auxiliary clock for PCIe
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- description: PIPE clock
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clock-names:
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minItems: 5
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items:
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- const: aclk_mst
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- const: aclk_slv
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- const: aclk_dbi
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- const: pclk
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- const: aux
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- const: pipe
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msi-map: true
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num-lanes: true
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phys:
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maxItems: 1
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phy-names:
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const: pcie-phy
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power-domains:
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maxItems: 1
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ranges:
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minItems: 2
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maxItems: 3
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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oneOf:
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- const: pipe
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- items:
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- const: pwr
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- const: pipe
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vpcie3v3-supply: true
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- msi-map
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- num-lanes
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- phys
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- phy-names
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- power-domains
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie3x2: pcie@fe280000 {
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compatible = "rockchip,rk3568-pcie";
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reg = <0x3 0xc0800000 0x0 0x390000>,
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<0x0 0xfe280000 0x0 0x10000>,
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<0x3 0x80000000 0x0 0x100000>;
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reg-names = "dbi", "apb", "config";
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bus-range = <0x20 0x2f>;
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clocks = <&cru 143>, <&cru 144>,
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<&cru 145>, <&cru 146>,
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<&cru 147>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux";
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device_type = "pci";
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linux,pci-domain = <2>;
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max-link-speed = <2>;
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msi-map = <0x2000 &its 0x2000 0x1000>;
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num-lanes = <2>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power 15>;
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ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
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<0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
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resets = <&cru 193>;
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reset-names = "pipe";
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#address-cells = <3>;
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#size-cells = <2>;
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};
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};
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...
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