76 lines
1.7 KiB
YAML
76 lines
1.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek PCIe PHY
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maintainers:
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- Jianjun Wang <jianjun.wang@mediatek.com>
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description: |
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The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
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properties:
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compatible:
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const: mediatek,mt8195-pcie-phy
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reg:
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maxItems: 1
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reg-names:
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items:
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- const: sif
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"#phy-cells":
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const: 0
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nvmem-cells:
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maxItems: 7
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description:
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Phandles to nvmem cell that contains the efuse data, if unspecified,
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default value is used.
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nvmem-cell-names:
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items:
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- const: glb_intr
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- const: tx_ln0_pmos
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- const: tx_ln0_nmos
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- const: rx_ln0
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- const: tx_ln1_pmos
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- const: tx_ln1_nmos
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- const: rx_ln1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- reg-names
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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phy@11e80000 {
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compatible = "mediatek,mt8195-pcie-phy";
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#phy-cells = <0>;
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reg = <0x11e80000 0x10000>;
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reg-names = "sif";
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nvmem-cells = <&pciephy_glb_intr>,
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<&pciephy_tx_ln0_pmos>,
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<&pciephy_tx_ln0_nmos>,
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<&pciephy_rx_ln0>,
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<&pciephy_tx_ln1_pmos>,
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<&pciephy_tx_ln1_nmos>,
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<&pciephy_rx_ln1>;
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nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
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"tx_ln0_nmos", "rx_ln0",
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"tx_ln1_pmos", "tx_ln1_nmos",
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"rx_ln1";
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power-domains = <&spm 2>;
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};
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