108 lines
2.8 KiB
YAML
108 lines
2.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. MSM8226 TLMM block
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm MSM8226 SoC.
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properties:
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compatible:
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const: qcom,msm8226-pinctrl
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reg:
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description: Specifies the base address and size of the TLMM register space
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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"#gpio-cells": true
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gpio-ranges: true
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gpio-reserved-ranges:
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maxItems: 1
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-msm8226-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-msm8226-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-msm8226-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-6])$"
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- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins. Functions are only valid for gpio pins.
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enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
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blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_spi1,
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blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
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blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1,
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gp0_clk, gp1_clk, sdc3, wlan ]
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required:
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- pins
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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msmgpio: pinctrl@fd510000 {
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compatible = "qcom,msm8226-pinctrl";
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reg = <0xfd510000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&msmgpio 0 0 117>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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serial-state {
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pins = "gpio8", "gpio9";
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function = "blsp_uart3";
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drive-strength = <8>;
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bias-disable;
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};
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};
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