126 lines
3.9 KiB
YAML
126 lines
3.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,qdu1000-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. QDU1000/QRU1000 TLMM block
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maintainers:
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- Melody Olvera <quic_molvera@quicinc.com>
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description: |
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Top Level Mode Multiplexer pin controller found in the QDU1000 and
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QRU1000 SoCs.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,qdu1000-tlmm
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reg:
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maxItems: 1
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interrupts: true
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 76
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gpio-line-names:
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maxItems: 151
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-qdu1000-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-qdu1000-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-qdu1000-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|150)$"
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- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ atest_char, atest_usb, char_exec, CMO_PRI, cmu_rng,
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dbg_out_clk, ddr_bist, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4,
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ddr_pxi5, ddr_pxi6, ddr_pxi7, eth012_int_n, eth345_int_n,
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gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_pps_in, hardsync_pps_in,
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intr_c, jitter_bist_ref, pcie_clkreqn, phase_flag, pll_bist,
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pll_clk, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable,
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qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
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qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss,
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qlink3_enable, qlink3_request, qlink3_wmss, qlink4_enable,
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qlink4_request, qlink4_wmss, qlink5_enable, qlink5_request,
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qlink5_wmss, qlink6_enable, qlink6_request, qlink6_wmss,
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qlink7_enable, qlink7_request, qlink7_wmss, qspi_clk, qspi_cs,
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qspi0, qspi1, qspi2, qspi3, qup00, qup01, qup02, qup03, qup04,
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qup05, qup06, qup07, qup08, qup10, qup11, qup12, qup13, qup14,
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qup15, qup16, qup17, qup20, qup21, qup22, SI5518_INT, smb_alert,
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smb_clk, smb_dat, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
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tgu_ch4, tgu_ch5, tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1,
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tmess_prng2, tmess_prng3, tod_pps_in, tsense_pwm1, tsense_pwm2,
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usb2phy_ac, usb_con_det, usb_dfp_en, usb_phy, vfr_0, vfr_1,
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vsense_trigger ]
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required:
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- pins
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl@f000000 {
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compatible = "qcom,qdu1000-tlmm";
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reg = <0xf000000 0x1000000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 151>;
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wakeup-parent = <&pdc>;
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uart0-default-state {
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pins = "gpio6", "gpio7", "gpio8", "gpio9";
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function = "qup00";
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};
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};
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