163 lines
4.8 KiB
YAML
163 lines
4.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sdm845-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SDM845 TLMM pin controller
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm SDM845 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,sdm845-pinctrl
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 75
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gpio-line-names:
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maxItems: 150
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sdm845-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sdm845-tlmm-state"
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additionalProperties: false
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"-hog(-[0-9]+)?$":
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required:
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- gpio-hog
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$defs:
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qcom-sdm845-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
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- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2,
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atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_usb13,
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atest_usb2, atest_usb20, atest_usb21, atest_usb22, atest_usb23,
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audio_ref, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
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cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
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cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
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ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
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gcc_gp2, gcc_gp3, gpio, jitter_bist, ldo_en, ldo_update,
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lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
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mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator, pci_e0,
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pci_e1, phase_flag, pll_bist, pll_bypassnl, pll_reset,
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pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable,
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qlink_request, qspi_clk, qspi_cs, qspi_data, qua_mi2s, qup0,
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qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3,
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qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
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sdc4_clk, sdc4_cmd, sdc4_data, sd_write, sec_mi2s, sp_cmu,
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spkr_i2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
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tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
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tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
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tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
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uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
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uim_batt, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
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wlan1_adc1, wlan2_adc0, wlan2_adc1]
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required:
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- pins
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl@3400000 {
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compatible = "qcom,sdm845-pinctrl";
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reg = <0x03400000 0xc00000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 151>;
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wakeup-parent = <&pdc_intc>;
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ap-suspend-l-hog {
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gpio-hog;
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gpios = <126 GPIO_ACTIVE_LOW>;
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output-low;
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};
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cci0-default-state {
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pins = "gpio17", "gpio18";
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function = "cci_i2c";
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bias-pull-up;
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drive-strength = <2>;
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};
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cam0-default-state {
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rst-pins {
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pins = "gpio9";
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function = "gpio";
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drive-strength = <16>;
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bias-disable;
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};
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mclk0-pins {
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pins = "gpio13";
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function = "cam_mclk";
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drive-strength = <16>;
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bias-disable;
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};
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};
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};
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